IP Library Granted Patent US 7,687,303
Granted Patent B1
US 7,687,303 · App. 11/264,930 · Granted Mar 30, 2010

Method for determining via/contact pattern density effect in via/contact etch rate

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Quick Facts
Patent No.
US 7,687,303
App. No.
11/264,930
Granted
Mar 30, 2010
Kind
B1
Abstract

A method for determining an effect of via/contact pattern density in via/contact etch rate of a wafer includes determining a neutral etchant species number flux intersecting each via/contact mouth as a function of local layout characteristics and determining variations in the neutral etchant species flux number as a function of the via/contact pattern density in a wafer scale. The comparison of these number fluxes provides the capability to discriminate an underetched or an overetched via/contact from normal vias/contacts satisfying an etch tolerance criterion. Chip designers can modify the layout design to minimize via/contact failures. Chip manufacturers can modify the etching process to minimize via/contact failures.

Claims (272)

1. A method for improving wafer yield in response to analysis of effects of via or contact pattern density on via or contact etch rate of a wafer, comprising the steps of:

(a) determining a neutral etchant species number flux intersecting each via or each contact mouth as a function of local layout characteristics;

(b) determining variations in a neutral etchant species concentration as a function of the via or contact pattern density in a via or a contact layout; and

(c) adjusting the layout and etching process to reduce via failures.

2. The method for improving wafer yield according to claim 1 , further comprising identifying underetched or overetched vias or contacts.

3. The method for improving wafer yield according to claim 1 , wherein the determining step (a) comprises:

(a1) calculating a region of intersection (r) of solid angle, through which neutral etchant species have a line of sight access to a via j or contact j mouth, with an effective reactive surface situated at a distance λ above a wafer surface, wherein λ is a mean free path;

(a2) generating a circle with a radius equal to 2 r around the via or the contact j ;

(a3) counting a number of vias or contacts (n r ) located inside the 2 r -circle;

(a4) generating circles of radius equal to r around via or contact centers of each via or contact located inside the 2 r -circle;

(a5) calculating areas of overlap between the r-circle of a center via or contact in the 2 r -circle and r-circles of the rest of the vias or contacts in the 2 r -circle;

(a6) calculating a sum (S j ) of the areas of overlap with a weighting factor of 1/k, wherein k is a number of overlapped r-circles;

(a7) calculating S j for all vias or contacts in the layout; and

(a8) calculating an incident neutral flux (Γ j ) crossing the mouth of the via or contact j .

4. The method for improving wafer yield according to claim 3 , wherein for the calculating step (a1),

r

=

2

λ

AR

,

wherein AR is a via or contact aspect ration, wherein

AR

=

h

PR

+

h

Me

+

h

Via

d

Via

,

wherein h PR is a thickness of a photoresist layer, h Me is a thickness of a metal layer, h Via is a thickness of a via or contact height, and d Via is a via or contact diameter.

5. The method for improving wafer yield according to claim 3 , wherein for the calculating step (a6),

S

j

=

k

=

1

n

1

k

S

k

,

wherein n is a number of vias or contacts located inside the 2 r -circle, and S k is an area of the k-overlapped regions.

6. The method for improving wafer yield according to claim 3 , wherein for the calculating step (a8), Γ j =Γ n S j , wherein Γ n is a total number flux consumed by all a wafer regions containing n vias or contacts.

7. The method for improving wafer yield according to claim 1 , wherein the determining step (b) comprises:

(b1) calculating a total neutral flux consumption (Γ m ) by a sub-region of the wafer;

(b2) determining a neutral etchant species concentration (N m ) of m number of vias or contacts in the sub-region;

(b3) determining a neutral etchant species concentration (ζ 0 ) near a wafer edge; and

(b4) solving a system of linear equations to derive neutral concentrations (ζ i ) for every i th sub-region.

8. The method for improving wafer yield according to claim 7 , wherein for the calculating step (b1),

Γ

m

Γ

o

(

δ

Ω

2

π

)

S

mk

eff

N

m

c

_

4

1

2

π

(

Θ

λ

2

)

S

mk

eff

=

N

m

c

_

ΘmS

8

πλ

2

k

eff

=

φ

m

N

m

,

wherein m is a number of vias or contacts in the sub-region, δΩ is a solid angle through which via j or contact j mouth is “visible” from a flux generating point located at an effective reactive surface, Θ is an area of the via j or the contact mouth, S Σ is a total area covered by m r-circles corresponding to m vias or contacts, c is a gas thermal velocity, k eff is a coefficient describing a probability that radicals penetrating a via or contact mouth are consumed by etch reactions, and λ is a mean free path.

9. The method for improving wafer yield according to claim 7 , wherein for the determining step (b2), a mass balance equation for the sub-regions is

2

L

λ

2

γ

-

Γ

m

-

2

L

λ

D

k

=

1

4

(

N

m

-

N

m

k

λ

=

0

,

wherein 2L is an electrode gap in a capacitive coupled plasma reactor, or the characteristic size of the plasma region in vertical direction for any other type of plasma reactor, γ is a rate of homogeneous generation of neutral etchant species in a discharge, N mk is a neutral species concentration in a 4 neighbor sub-regions, D is a diffusion coefficient of neutrals, and λ is a mean free path, wherein the mass balance equation can be modified to the system of linear equations:

ξ

m

(

φ

m

2

LD

+

4

)

-

k

=

1

4

ξ

m

k

=

1

,

where

ξ

i

=

N

i

D

γ

λ

2

and

φ

m

=

c

_

Θ

mS

8

π

λ

2

k

eff

.

10. The method for improving wafer yield according to claim 7 , wherein for the determining step (b3),

ξ

o

=

S

w

-

n

d

S

d

λ

2

Q

2

LD

,

wherein S w is a wafer area, S d is an area of a single die, Q is an inlet feed gas flow rate, 2L is an inter-electrode gap, or the characteristic size of a plasma region in a vertical direction for any other type of the plasma reactor, n d is a number of dies on a wafer, and λ is a mean free path.

11. The method for improving wafer yield according to claim 1 wherein the determining step (a) comprises the calculation of relative fluxes of neutral etchant species intersecting each via/contact mouth.

12. The method for improving wafer yield according to claim 11 further comprising a comparison of said relative fluxes to discriminate under-etched or over-etched vias/contacts from the normal ones satisfying the etch tolerance criterion.

Assignments (3)
MERGER AND CHANGE OF NAME Recorded Jun 16, 2021
From: MENTOR GRAPHICS CORPORATION; SIEMENS INDUSTRY SOFTWARE INC.
To: SIEMENS INDUSTRY SOFTWARE INC.
Reel/Frame 056597/0234 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2008
From: PONTE SOLUTIONS, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 021240/0653 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2005
From: SUKHAREV, VALERIY; MARKOSIAN, ARA
To: PONTE SOLUTIONS, INC.
Reel/Frame 017187/0347 →