Patent Assignment
Reel/Frame 056597/0234
Merger and Change of Name
Recorded: 2021-06-16
Pages: 7
Assignors
MENTOR GRAPHICS CORPORATION
Executed: 2020-12-30
SIEMENS INDUSTRY SOFTWARE INC.
Executed: 2020-12-30
Assignee
SIEMENS INDUSTRY SOFTWARE INC.
5800 GRANITE PARKWAY, SUITE 600, PLANO, TEXAS, 75024
Covered Properties
(86)
Circuit Comparison by Information Loss Matching
Patent:
7,222,317 →
Application:
10/822,166 →
Memory Repair Circuit and Method
Circuit and Method for Measuring Delay of High Speed Signals
Method and Apparatus for Steady State Analysis of a Voltage Controlled Oscillator
Patent:
7,332,974 →
Application:
11/045,241 →
Clocking Methodology for at-Speed Testing of Scan Circuits with Synchronous Clocks
Performing Opc on Structures with Virtual Edges
System, Method and Computer Program Product for Equivalence Checking Between Designs with Sequential Differences
Patent:
7,350,168 →
Application:
11/129,238 →
Distributed Electronic Design Automation Architecture
Dense Opc
Queuing Methods for Distributing Programs for Producing Test Data
Methods for Distributing Programs for Generating Test Data
Methods for Distribution of Test Generation Programs
Method for Determining via/Contact Pattern Density Effect in via/Contact Etch Rate
Patent:
7,687,303 →
Application:
11/264,930 →
Integrated Circuits with Reduced Leakage Current
System, Method and Computer Program Product for Word-Level Numerical Computations and Storage
Patent:
7,333,032 →
Application:
11/335,928 →
Multi-Dimensional Analysis for Predicting Ret Model Accuracy
Capacitance Extraction of Intergrated Circuits with Floating Fill
Dram Density Enhancements
Clock Model for Formal Verification of a Digital Circuit Description
Method for at-Speed Testing of Memory Interface Using Scan
Single-Poly Non-Volatile Memory Cell
System, Method and Computer Program Product for Timing-Independent Sequential Equivalence Verification
Patent:
7,607,115 →
Application:
11/538,751 →
System and Computer Program Product for Simultaneous Cell Identification/Technology Mapping
Patent:
7,539,956 →
Application:
11/601,272 →
Selective Shielding for Multiple Exposure Masks
Data Preparation for Multiple Mask Printing
Generating a Convergent Circuit Design from a Functional Description Using Entities Having Access to the Functional Description and to Physical Design Information
Dual Metric Opc
Pre-Bias Optical Proximity Correction
Ic Chip at-Functional-Speed Testing with Process Coverage Evaluation
One-Time-Programmable Memory
Ic Layout Parsing for Multiple Masks
Circuit Design Optimization of Integrated Circuit Based Clock Gated Memory Elements
System and Method for Increasing Error Checking Performance by Calculating Crc Calculations After Multiple Test Patterns for Processor Design Verification and Validation
System and Method of Testing Using Test Pattern Re-Execution in Varying Timing Scenarios for Processor Design Verification and Validation
System and Method for Modeling Stochastic Behavior of a System of N Similar Statistical Variables
Design Method and System for Minimizing Blind via Current Loops
Clock Distribution Network Wiring Structure
Integrated Circuit Design System, Method, and Computer Program Product That Takes into Account Observability Based Clock Gating Conditions
Patent:
7,761,827 →
Application:
11/832,425 →
Integrated Circuit Design System, Method, and Computer Program Product That Takes into Account the Stability of Various Design Signals
Patent:
7,966,593 →
Application:
11/832,443 →
Hardware Verification Batch Computing Farm Simulator
Method and Apparatus for Detecting Clock Gating Opportunities in a Pipelined Electronic Circuit Design
Simultaneous Power and Timing Optimization in Integrated Circuits by Performing Discrete Actions on Circuit Components
Device, System and Method for Formal Verification
Dram with Hybrid Sense Amplifier
Layout Optimization Using Parameterized Cells
Systems, Methods and Computer Products for Traversing Schematic Hierarchy Using a Scrolling Mechanism
Method and Apparatus for Storing and Distributing Memory Repair Information
Method for Eliminating Negative Slack in a Netlist via Transformation and Slack Categorization
Scalable Dependent State Element Identification
Method for Faster Identification of Available Reference Designators in a Design Automation System
Optimal Simplification of Constraint-Based Testbenches
Method and Apparatus for Incrementally Computing Criticality and Yield Gradient
Buffer Placement with Respect to Data Flow Direction and Placement Area Geometry in Hierarchical Vls Designs
Reliability Evaluation and System Fail Warning Methods Using on Chip Parametric Monitors
Method and System for Developing Post-Layout Electronic Data Automation (Eda) Applications
Method and System for Representing Geometrical Layout Design Data in Electronic Design Systems
Method and System for Processing Geometrical Layout Design Data
System and Method of Automating the Addition of Rtl Based Critical Timing Path Counters to Verify Critical Path Coverage of Post-Silicon Software Validation Tools
Defining and recording threshold-qualified count events of a simulation by testcases
System and Method for Generating at-Speed Structural Tests to Improve Process and Environmental Parameter Space Coverage
Arrangements for Developing Integrated Circuit Designs
Obtaining Bounds on Process Parameters for Opc-Verification
Optimal Timing-Driven Cloning Under Linear Delay Model
Auto-Routing Small Jog Eliminator
Incremental Timing-Driven, Physical-Synthesis Using Discrete Optimization
Method and Computer Program for Selecting Circuit Repairs Using Redundant Elements with Consideration of Aging Effects
Method for Incremental, Timing-Driven, Physical-Synthesis Optimization Under a Linear Delay Model
Method for Determining Features Associated with Fails of Integrated Circuits
Sequential Equivalence Checking for Asynchronous Verification
Automatic Verification of Adequate Conductive Return-Current Paths
Automated Optimization of Device Structure During Circuit Design Stage
Adaptive Weighting Method for Layout Optimization with Multiple Priorities
Method of Reducing Crosstalk Induced Noise in Circuitry Designs
Parallel Simulation Using an Ordered Priority of Event Regions
Shape-Based Photolithographic Model Calibration
Dense Read-Only Memory
Automatic Bus Routing
Resource Remapping in a Hardware Emulation Environment
Testing in a Hardware Emulation Environment
Decoder with Memory
Single-Poly Non-Volatile Memory Cell
Efficient Xor Calculation
System and Method for Power Reduction Through Power Aware Latch Weighting
Controlling real time during embedded system development
Cross-Bar Switching in an Emulation Environment
Modeling and Simulation Method
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Apr 9, 2004
From: MATHUR, ANMOL; GOYAL, DEEPAK
To: CALYPTO DESIGN SYSTEMS
Reel/Frame 015213/0928 →
Assignment of Assignor's Interest
Jun 16, 2004
From: NADEAU-DOSTIE, BENOIT; ADHAM, SAMAN M. I.
To: LOGICVISION, INC.
Reel/Frame 015481/0937 →
Assignment of Assignor's Interest
Nov 19, 2004
From: SUNTER, STEPHEN K.; ROY, AUBIN P.J.
To: LOGICVISION, INC.
Reel/Frame 016018/0534 →
Assignment of Assignor's Interest
Jan 27, 2005
From: MEHROTRA, AMIT; NARAYAN, AMIT
To: BERKELEY DESIGN AUTOMATION, INC.
Reel/Frame 016231/0136 →
Assignment of Assignor's Interest
Feb 18, 2005
From: NADEAU-DOSTIE, BENOIT; COTE, JEAN-FRANCOIS; MAAMARI, FADI
To: LOGICVISION, INC.
Reel/Frame 016310/0452 →
Assignment of Assignor's Interest
May 12, 2005
From: MATHUR, ANMOL; SHARMA, NIKHIL; GOYAL, DEEPAK; HASTEER, GAGAN
To: CALYPTO DESIGN SYSTEMS, INC.
Reel/Frame 016573/0023 →
Assignment of Assignor's Interest
Jun 2, 2005
From: WORD, JAMES
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 016090/0296 →
Assignment of Assignor's Interest
Sep 13, 2005
From: MENTOR GRAPHICS (INDIA) PRIVATE LTD.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 016992/0813 →
Assignment of Assignor's Interest
Sep 13, 2005
From: SANGEM, VENKANNA; MANDAVILLI, SRINIVAS; AKELLA, CHANDRA SEKHAR
To: MENTOR GRAPHICS (INDIA) PRIVATE LTD.
Reel/Frame 016992/0600 →
Assignment of Assignor's Interest
Nov 1, 2005
From: SUKHAREV, VALERIY; MARKOSIAN, ARA
To: PONTE SOLUTIONS, INC.
Reel/Frame 017187/0347 →
Assignment of Assignor's Interest
Dec 14, 2005
From: COBB, NICOLAS BAILEY; DUDAU, DRAGOS
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 016931/0186 →
Assignment of Assignor's Interest
Dec 28, 2005
From: UDELL, JON; WANG, CHEN; KASSAB, MARK; RAJSKI, JANUSZ
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 016948/0378 →
Assignment of Assignor's Interest
Dec 28, 2005
From: UDELL, JON
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 016948/0552 →
Assignment of Assignor's Interest
Dec 28, 2005
From: UDELL, JON; WANG, CHEN; KASSAB, MARK; RAJSKI, JANUSZ
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 016948/0444 →
Assignment of Assignor's Interest
Jan 20, 2006
From: RAMACHANDRAN, VENKY; HALDAR, MALAY
To: CALYPTO DESIGN SYSTEMS, INC.
Reel/Frame 017500/0170 →
Corrective Assignment to Correct the Assignee Address. Previously Recorded on Reel 016992 Frame 0813.
Feb 9, 2006
From: MENTOR GRAPHICS (INDIA) PRIVATE LTD.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 017554/0255 →
Assignment of Assignor's Interest
Mar 16, 2006
From: AFGHAHI, MORTEZA; TERZIOGLU, ESIN; WINOGRAD, GIL I.
To: NOVELICS
Reel/Frame 017318/0055 →
Assignment of Assignor's Interest
Apr 12, 2006
From: AL-IMAM, MOHAMED; FATHY, RAMI
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 017462/0175 →
Assignment of Assignor's Interest
May 18, 2006
From: SEAWRIGHT, JAMES ANDREW GARRARD; LEVITT, JEREMY RUTLEDGE; GAUTHRON, CHRISTOPHE
To: MENTOR GRAPHICS CORP.
Reel/Frame 017922/0782 →
Assignment of Assignor's Interest
Oct 16, 2006
From: TERZIOGLU, ESIN; WINOGRAD, GIL I.; AFGHAHI, MORTEZA CYRUS
To: NOVELICS LLC
Reel/Frame 018393/0053 →
Security Agreement
Jun 9, 2008
From: BERKELEY DESIGN AUTOMATION, INC.
To: SILICON VALLEY BANK
Reel/Frame 021064/0486 →
Assignment of Assignor's Interest
Jun 27, 2008
From: GURNEY, DAVID J
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 021164/0824 →
Security Interest
Jun 30, 2008
From: BERKELEY DESIGN AUTOMATION, INC.
To: VENTURE LENDING & LEASING V, INC., AS AGENT
Reel/Frame 021185/0907 →
Assignment of Assignor's Interest
Jul 15, 2008
From: PONTE SOLUTIONS, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 021240/0653 →
Security Agreement
Nov 3, 2008
From: CALYPTO DESIGN SYSTEMS, INC.
To: SILICON VALLEY BANK
Reel/Frame 021773/0206 →