IP Library Granted Patent US 7,612,583
Granted Patent B2
US 7,612,583 · App. 12/131,920 · Granted Nov 3, 2009

Efficient XOR calculation

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Quick Facts
Patent No.
US 7,612,583
App. No.
12/131,920
Granted
Nov 3, 2009
Kind
B2
Abstract

In one embodiment, an exclusive-OR (XOR) calculation circuit configured to XOR a plurality of N input signals ranging from a first signal to an Nth signal is provided. The calculation circuit includes: a plurality of logic circuits arranged from a first logic circuit to a last logic circuit, wherein each logic circuit is configured to receive two logical input signals and the complement of the two logical input signals and to provide an XOR output signal and an XNOR output signal, wherein the XOR output signal represents the XOR of its two input signals and the XNOR output signal represents an exclusive-NOT-OR (XNOR) of its two input signals, and wherein the first logic circuit receives two of the N input signals as its logical input signals, a second logic circuit receives another one of the N input signals and an XOR output signal from the first logic circuit as its logical input signals, and so on such that the last logic circuit receives a remaining one of the N input signals and an XOR output signal from a next-to-last logic circuit as its logical input signals.

Claims (2)

1. An exclusive-OR (XOR) calculation circuit configured to XOR a plurality of N input signals ranging from a first signal to an Nth signal, comprising:

a plurality of logic circuits arranged from a first logic circuit to a last logic circuit, wherein each logic circuit is configured to receive two logical input signals and the complement of the two logical input signals and to provide an XOR output signal and an XNOR output signal, wherein the XOR output signal represents the XOR of its two input signals and the XNOR output signal represents an exclusive-NOT-OR (XNOR) of its two input signals, and wherein the first logic circuit receives two of the N input signals as its logical input signals, a second logic circuit receives another one of the N input signals and an XOR output signal from the first logic circuit as its logical input signals, and so on such that the last logic circuit receives a remaining one of the N input signals and an XOR output signal from a next-to-last logic circuit as its logical input signals.

Assignments (4)
MERGER AND CHANGE OF NAME Recorded Jun 16, 2021
From: MENTOR GRAPHICS CORPORATION; SIEMENS INDUSTRY SOFTWARE INC.
To: SIEMENS INDUSTRY SOFTWARE INC.
Reel/Frame 056597/0234 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2011
From: NOVELICS CORPORATION
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 026306/0510 →
CHANGE OF NAME Recorded May 17, 2011
From: NOVELICS, LLC
To: NOVELICS CORPORATION
Reel/Frame 026293/0263 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2008
From: WINOGRAD, GIL I.
To: NOVELICS, LLC
Reel/Frame 021384/0150 →