IP Library Granted Patent US 7,333,032
Granted Patent B1
US 7,333,032 · App. 11/335,928 · Granted Feb 19, 2008

System, method and computer program product for word-level computations and storage

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Quick Facts
Patent No.
US 7,333,032
App. No.
11/335,928
Granted
Feb 19, 2008
Kind
B1
Abstract

A system, method and computer program product are provided for generating and manipulating a compressed data structure. Initially, a plurality of values associated with an ordered collection of bits is received. It is then determined which of the values are the same. To this end, a compressed data structure including the values is generated, based on the determination.

Claims (45)

1. A method, comprising:

receiving a plurality of values associated with an ordered collection of bits;

determining which of the values are the same;

generating a compressed data structure including the values, based on the determination; and

generating a plurality of resulting values based on one or more arithmetic or logical operations performed on the plurality of values associated with the ordered collection of bits;

wherein the ordered collection of bits is associated with a register transfer level (RTL) design.

2. The method of claim 1 , wherein the ordered collection of bits includes a word.

3. The method of claim 1 , wherein each value is associated with at least one of the bits.

4. The method of claim 1 , wherein a single value is associated with a plurality of the bits.

5. The method of claim 1 , wherein the ordered collection of bits represents a plurality of aspects of a bus.

6. The method of claim 5 , wherein the values represent a delay associated with each of a plurality of bits of the bus.

7. The method of claim 5 , wherein the values represent a switching activity associated with each of a plurality of bits of the bus.

8. The method of claim 1 , wherein the ordered collection of bits represents a multi-bit instance.

9. The method of claim 8 , wherein the values represent a leakage power associated with the instance.

10. The method of claim 8 , wherein the ordered collection of bits further represents a port of the multi-bit instance.

11. The method of claim 10 , wherein the values represent arrival times associated with each of a plurality of bits of the port.

12. The method of claim 10 , wherein the values represent required times associated with each of a plurality of bits of the port.

13. The method of claim 1 , wherein the determination is utilized for identifying unique values.

14. The method of claim 13 , wherein only the unique values are stored in the compressed data structure.

15. The method of claim 14 , wherein the compressed data structure includes only a portion of the identified unique values.

16. The method of claim 14 , wherein the compressed data structure includes all of the identified unique values.

17. The method of claim 14 , wherein the compressed data structure includes a user-configured amount of the unique values.

18. The method of claim 1 , and further comprising reducing a number of arithmetic or logical operations involving a plurality of the data structures.

19. The method of claim 1 , and further comprising reducing a number of user specified functions involving a plurality of the data structures.

20. The method of claim 1 , and further comprising generating a mapping for identifying groups in association with the ordered collections of bits.

21. The method of claim 1 , wherein one of a mathematical and a logical operation is performed on a plurality of compressed data structures to produce a single compressed data structure result.

22. The method of claim 1 , wherein the resulting values include first resulting values, and second resulting values are generated based on a second arithmetic or logical operation performed on the first resulting values.

23. A computer program product embodied on a computer readable medium, comprising:

computer code for receiving a plurality of values associated with an ordered collection of bits;

computer code for determining which of the values are the same;

computer code for generating a compressed data structure including the values, based on the determination; and

computer code for generating a plurality of resulting values based on one or more arithmetic or logical operations performed on the plurality of values associated with the ordered collection of bits;

wherein the ordered collection of bits is associated with a register transfer level (RTL) design.

24. A data structure system embodied on a computer readable medium, comprising:

a compressed data structure including a plurality of values associated with an ordered collection of bits which are compressed based on a determination as to which the values are the same;

wherein a plurality of resulting values are generated based on one or more arithmetic or logical operations performed on the plurality of values associated with the ordered collection of bits;

wherein the ordered collection of bits is associated with a register transfer level (RTL) design.

25. A method, comprising:

receiving a plurality of input values associated with an ordered collection of bits; and

generating a plurality of resulting values based on one or more arithmetic or logical operations performed on the plurality of input values;

wherein the ordered collection of bits is associated with a register transfer level (RTL) design.

26. The method of claim 25 , wherein only unique values in the plurality of resulting values are included in a compressed data structure, and a mapping is created for identifying groups in association with the ordered collection of bits.

27. The method of claim 26 , wherein the compressed data structure includes a user-configured amount of the unique values.

28. The method of claim 25 , wherein a single group is mapped to a plurality of ordered collections of bits.

29. The method of claim 25 , and further comprising reducing a number of the arithmetic or logical operations by utilizing compressed data structures associated with the input values.

Assignments (5)
MERGER AND CHANGE OF NAME Recorded Jun 16, 2021
From: MENTOR GRAPHICS CORPORATION; SIEMENS INDUSTRY SOFTWARE INC.
To: SIEMENS INDUSTRY SOFTWARE INC.
Reel/Frame 056597/0234 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2018
From: CALYPTO DESIGN SYSTEMS, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 047766/0077 →
RELEASE Recorded Aug 24, 2011
From: SILICON VALLEY BANK
To: CALYPTO DESIGN SYSTEMS, INC.
Reel/Frame 026803/0962 →
SECURITY AGREEMENT Recorded Nov 3, 2008
From: CALYPTO DESIGN SYSTEMS, INC.
To: SILICON VALLEY BANK
Reel/Frame 021773/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 20, 2006
From: RAMACHANDRAN, VENKY; HALDAR, MALAY
To: CALYPTO DESIGN SYSTEMS, INC.
Reel/Frame 017500/0170 →