Single-poly non-volatile memory cell
View Patent ↗A non-volatile memory cell includes a floating gate transistor having a floating gate coupled to a metal layer capacitor defined in one or more metal layers. Within each metal layer, the metal layer capacitor includes a first plate coupled to the floating gate and a second plate separated from the first plate by a fringe capacitance junction.
1. A memory array, comprising:
a substrate including diffusion regions for a plurality of floating gate transistors; the floating gate transistors being arranged in rows;
a middle metal conductor extending along each row; each middle metal conductor being defined in at least one metal layer adjacent the substrate; and
a shared metal conductor extending between each pair of adjacent rows, each shared metal conductor being defined in the at least one metal layer;
wherein each floating gate transistor has a gate coupled to a capacitor, each capacitor including two anode plates being defined in the at least one metal layer, the two anode plates sandwiching the middle metal conductor corresponding to the floating gate transistor's row, each capacitor having three cathodes formed by the sandwiched middle conductor and a pair of shared metal conductors adjacent to the floating gate transistor's row.
2. The memory array of claim 1 , wherein for each row, the middle metal conductor and the shared metal conductors are defined in a plurality of metal layer coupled together by vias.
3. The memory array of claim 2 , wherein for each row, the anode plates are defined in a plurality of metal layers coupled together by vias.
4. The memory array of claim 3 , wherein each floating gate transistor is arranged in a corresponding memory cell including a select gate transistor, the memory cells in each row being arranged in pairs such that each select gate transistor in each pair couples to a common bit line.
5. The memory array of claim 4 , further comprising a first word line and a second word line for each row, the first word line being coupled to a select gate for a first select gate transistor in each pair, the second word line being coupled to a select gate for a remaining second select gate transistor in each pair.
6. The memory array of claim 1 , wherein each anode plate is substantially rectangular.
7. A method of programming an NMOS non-volatile memory having an array of memory cells arranged in rows, each memory cell having a floating gate transistor including a terminal coupled to an erase line, wherein a middle metal conductor extends along each row; each middle metal conductor being defined in at least one metal layer adjacent a substrate; and wherein a shared metal conductor extends between each pair of adjacent rows, each shared metal conductor being defined in the at least one metal layer, and wherein each floating gate transistor has a gate coupled to a capacitor, each capacitor including two anode plates being defined in the at least one metal layer, the two anode plates sandwiching the middle metal conductor corresponding to the floating gate transistor's row, each capacitor having three cathodes formed by the sandwiched middle conductor and a pair of shared metal conductors adjacent to the floating gate transistor's row, comprising:
for a given memory cell, grounding the erase line coupled to the memory cell's floating gate transistor; and
for a row including the given memory cell, charging the row's middle metal conductor and the pair of shared metal conductors adjacent to the row to a positive programming voltage such that the given memory cell is programmed.
8. The method of claim 7 , further comprising erasing the programmed non-volatile memory cell by grounding the row's middle metal conductor and the pair of shared metal conductors and charging the erase line to the positive programming voltage.