Optimal simplification of constraint-based testbenches
View Patent ↗Methods and systems are provided for determining redundancies in a system model such as a complex circuit design including gates that are state components. A candidate redundant gate is selected, and a merged model is built that eliminates the candidate redundant gate. If the candidate redundant gate is within the merged constraint cone the pre-merge model is used to validate redundancy of the candidate redundant gate. However, if the candidate redundant gate is not within the merged constraint cone the merged model is instead used to validate redundancy of the candidate redundant gate.
1. A method executed on a computer for simplifying verification of a circuit design represented by a model with constraints, said circuit design being a pre-merge design, the method comprising:
identifying a set of candidate redundant gates in the pre-merge design;
merging an arbitrary subset of the candidate redundant gates to create a merged design;
performing a verification process on the merged design; and
storing an output of the verification process in a machine readable medium accessible by said computer;
in response to determining that a property of the merged design is incorrect and identifying a failure scenario with said property, attempting to map the failure scenario on the merged design to a corresponding failure scenario on the pre-merge design; and
in response to successfully mapping the failure scenario of the merged design to a corresponding failure scenario on the pre-merge design, reporting that a corresponding property of the pre-merge design.
2. The method of claim 1 , further comprising:
in response to determining that a property of the merged design is correct, reporting that a corresponding property is correct for the pre-merge design.
3. The method of claim 1 , further comprising:
in response to an inability to successfully map the failure scenario of the merged design to a corresponding failure scenario on the pre-merge design, refining the merged model by eliminating a subset of causal merges.
4. The method of claim 1 , further comprising:
adding a replicated constraint cone, wherein the replicated constraint cone replicates a combinational fanin of the constraints.
5. The method of claim 1 , further comprising:
building a composite model including the pre-merge design and the merged design.
6. The method of claim 5 , further comprising:
adding equivalence-checking gates to inputs to check equivalence of a set of common signals to both the pre-merge model and the merged model;
wherein said verification process assesses the equivalence-checking gates over a set of signals common to the pre-merge design and the merged design.
7. A software product comprising a machine readable medium including a program of instructions for simplifying verification of a pre-merge design with constraints, wherein the program of instructions upon being executed on a computer causes the computer to perform activities comprising:
identifying a set of candidate redundant gates in the pre-merge design;
merging an arbitrary subset of the candidate redundant gates to create a merged design;
performing a verification process on the merged design; and
storing an output of the verification process in a machine readable medium accessible by said computer;
in response to determining that a property of the merged design is incorrect and identifying a failure scenario with said property, attempting to map the failure scenario on the merged design to a corresponding failure scenario on the pre-merge design; and
in response to successfully mapping the failure scenario of the merged design to a corresponding failure scenario on the pre-merge design, reporting that a corresponding property of the pre-merge design.
8. The software product of claim 7 , further comprising:
in response to determining that a property of the merged design is correct, reporting that a corresponding property is correct for the pre-merge design.
9. The software product of claim 7 , further comprising:
in response to an inability to successfully map the failure scenario of the merged design to a corresponding failure scenario on the pre-merge design, refining the merged model by eliminating a subset of causal merges.
10. The software product of claim 7 , further comprising:
adding a replicated constraint cone, wherein the replicated constraint cone replicates a combinational fanin of the constraints.
11. The software product of claim 10 , further comprising:
building a composite model including the pre-merge design and the merged design.
12. The software product of claim 11 , further comprising:
adding equivalence-checking gates to inputs to check equivalence of a set of common signals to both the pre-merge model and the merged model;
wherein said verification process assesses the equivalence-checking gates over a set of signals common to the pre-merge design and the merged design.