Patent Assignment
Reel/Frame 029733/0156
Assignment of Assignor's Interest
Recorded: 2013-02-01
Pages: 13
Assignor
INTERNATIONAL BUSINESS MACHINES CORPORATION
Executed: 2012-12-31
Assignee
MENTOR GRAPHICS CORPORATION
8005 SW BOECKMAN ROAD, WILSONVILLE, OREGON, 97070-7777
Covered Properties
(192)
Determining a Minimum Size of Presentation Data
Ic Chip at-Functional-Speed Testing with Process Coverage Evaluation
Circuit Design Optimization of Integrated Circuit Based Clock Gated Memory Elements
Method, Computer Program, Apparatus and System Providing Printing for an Illumination Mask for Three-Dimensional Images
System and Method for Increasing Error Checking Performance by Calculating Crc Calculations After Multiple Test Patterns for Processor Design Verification and Validation
System and Method of Testing Using Test Pattern Re-Execution in Varying Timing Scenarios for Processor Design Verification and Validation
System and Method for Modeling Stochastic Behavior of a System of N Similar Statistical Variables
Design Method and System for Minimizing Blind via Current Loops
Clock Distribution Network Wiring Structure
Hardware Verification Batch Computing Farm Simulator
Augmenting of Automated Clustering-Based Trace Sampling Methods by User-Directed Phase Detection
Method and Apparatus for Detecting Clock Gating Opportunities in a Pipelined Electronic Circuit Design
Simultaneous Power and Timing Optimization in Integrated Circuits by Performing Discrete Actions on Circuit Components
Device, System and Method for Formal Verification
Layout Optimization Using Parameterized Cells
Systems, Methods and Computer Products for Traversing Schematic Hierarchy Using a Scrolling Mechanism
Method for Eliminating Negative Slack in a Netlist via Transformation and Slack Categorization
Scalable Dependent State Element Identification
Method for Faster Identification of Available Reference Designators in a Design Automation System
Optimal Simplification of Constraint-Based Testbenches
Method and Apparatus for Incrementally Computing Criticality and Yield Gradient
Buffer Placement with Respect to Data Flow Direction and Placement Area Geometry in Hierarchical Vls Designs
Reliability Evaluation and System Fail Warning Methods Using on Chip Parametric Monitors
Methods and System for Analysis and Management of Parametric Yield
System and Method of Automating the Addition of Rtl Based Critical Timing Path Counters to Verify Critical Path Coverage of Post-Silicon Software Validation Tools
Defining and recording threshold-qualified count events of a simulation by testcases
Reporting Temporal Information Regarding Count Events of a Simulation
System and Method for Generating at-Speed Structural Tests to Improve Process and Environmental Parameter Space Coverage
Arrangements for Developing Integrated Circuit Designs
Obtaining Bounds on Process Parameters for Opc-Verification
Optimal Timing-Driven Cloning Under Linear Delay Model
Auto-Routing Small Jog Eliminator
Incremental Timing-Driven, Physical-Synthesis Using Discrete Optimization
Method and Computer Program for Selecting Circuit Repairs Using Redundant Elements with Consideration of Aging Effects
Method for Incremental, Timing-Driven, Physical-Synthesis Optimization Under a Linear Delay Model
Method for Determining Features Associated with Fails of Integrated Circuits
Sequential Equivalence Checking for Asynchronous Verification
Automatic Verification of Adequate Conductive Return-Current Paths
Automated Optimization of Device Structure During Circuit Design Stage
Adaptive Weighting Method for Layout Optimization with Multiple Priorities
Method of Reducing Crosstalk Induced Noise in Circuitry Designs
Ca Resistance Variability Prediction Methodology
Compact Model Methodology for Pc Landing Pad Lithographic Rounding Impact on Device Performance
Method and Apparatus for Evaluating Integrated Circuit Design Performance Using Enhanced Basic Block Vectors That Include Data Dependent Information
System and Method for Improved Hierarchical Analysis of Electronic Circuits
Method and Apparatus for Computing Test Margins for at-Speed Testing
Rendering a Mask Using Coarse Mask Representation
Calculating Image Intensity of Mask by Decomposing Manhattan Polygon Based on Parallel Edge
Placement Driven Routing
Auto-Router Performing Simultaneous Placement of Signal and Return Paths
Techniques for Filtering Systematic Differences from Wafer Evaluation Parameters
Multiple Voltage Threshold Timing Analysis for a Digital Integrated Circuit
Techniques for Modeling Variables in Subprograms of Hardware Description Language Programs
Method and Apparatus for Evaluating Integrated Circuit Design Model Performance Using Basic Block Vectors and Fly-by Vectors Including Microarchitecture Dependent Information
Modeling Spatial Correlations
Methods for Distributing a Random Variable Using Statistically-Correct Spatial Interpolation
Automated System and Processing for Expedient Diagnosis of Broken Shift Registers Latch Chains
Cmos Circuit Leakage Current Calculator
Method for Simplifying Tie Net Modeling for Router Performance
Generating Test Coverage Bin Based on Simulation Result
Systems and Methods Involving Designing Shielding Profiles for Integrated Circuits
Patent:
7,409,662 →
Application:
12/033,668 →
Control of Design Automation Process
Signal Phase Verification for Systems Incorporating Two Synchronous Clock Domains
Wire Structures Minimizing Coupling Effects Between Wires in a Bus
Method and Apparatus for Parallel Processing of Semiconductor Chip Designs
Arbitrary Waveform Propagation Through a Logic Gate Using Timing Analysis Results
Method to Identify Timing Violations Outside of Manufacturing Specification Limits
Exact Geometry Operations on Shapes Using Fixed-Size Integer Coordinates
Method for Testing Integrated Circuits
Identifying Sequential Functional Paths for Ic Testing Methods and System
Method and Apparatus for Improving Random Pattern Testing of Logic Structures
Methods for Conserving Memory in Statistical Static Timing Analysis
Method and System for Achieving Power Optimization in a Hierarchical Netlist
Methods for Practical Worst Test Definition and Debug During Block Based Statistical Static Timing Analysis
System and Method for Automated Analysis and Hierarchical Graphical Presentation of Application Results
Patent:
7,523,433 →
Application:
12/059,703 →
Techniques for Logic Built-in Self-Test Diagnostics of Integrated Circuit Devices
Method and System for Concurrent Buffering and Layer Assignment in Integrated Circuit Layout
Methods for Designing a Product Chip a Priori for Design Subsetting, Feature Analysis, and Yield Learning
Methods for Identifying Failing Timing Requirements in a Digital Design
System and Method of Predicting Problematic Areas for Lithography in a Circuit Design
Intersect Area Based Ground Rule for Semiconductor Design
Simultaneous Parameter-Driven and Deterministic Simulation with or Without Synchronization
Legalization of Vlsi Circuit Placement with Blockages Using Hierarchical Row Slicing
Data Correcting Hierarchical Integrated Circuit Layout Accommodating Compensate for Long Range Critical Dimension Variation
Apparatus and Method for Improved Test Controllability and Observability of Random Resistant Logic
Method of Circuit Power Tuning Through Post-Process Flattening
Method and Apparatus for Statistical Path Selection for at-Speed Testing
Method and Apparatus for Evaluating Integrated Circuit Design Performance Using Basic Block Vectors, Cycles Per Instruction (Cpi) Information and Microarchitecture Dependent Information
Method and Apparatus for Integrated Circuit Design Model Performance Evaluation Using Basic Block Vector Clustering and Fly-by Vector Clustering
Efficient Method for Locating a Short Circuit
Patent:
7,503,023 →
Application:
12/112,529 →
Test Case Generation with Backward Propagation of Predefined Results and Operand Dependencies
Method of Laying Out Integrated Circuit Design Based on Known Polysilicon Perimeter Densities of Individual Cells
Integrated Circuit with Uniform Polysilicon Perimeter Density, Method and Design Structure
Methods for Statistical Slew Propagation During Block-Based Statistical Static Timing Analysis
Method and System for Electromigration Analysis on Signal Wiring
System and Method for Auto-Routing Jog Elimination
Patent:
7,530,041 →
Application:
12/124,119 →
System and Method for Auto-Routing Jog Elimination
Patent:
7,530,042 →
Application:
12/124,120 →
Concurrently Modeling Delays Between Points in Static Timing Analysis Operation
Replicating Timing Data in Static Timing Analysis Operation
Incremental Speculative Merging
Method and System for Formal Verification of an Electronic Circuit Design
Method and System for Analyzing Cross-Talk Coupling Noise Events in Block-Based Statistical Static Timing
Method and Apparatus for Performing Logic Built-in Self-Testing of an Integrated Circuit
Method and System for Implementing Pattern Matching of Integrated Circuit Features Using Voronoi Diagrams
Computer Readable Medium, System and Associated Method for Designing Integrated Circuits with Loop Insertions
Methods, Systems and Computer Program Products for Layout Device Matching Driven by a Schematic Editor
Systems and Methods Involving Designing Integrated Circuits
Application:
12/164,642 →
Publication:
US 2009/0210844
Techniques for Performing a Logic Built-in Self-Test in an Integrated Circuit Device
Routing of Wires of an Electronic Circuit
Wiring Methods to Reduce Metal Variation Effects on Launch-Capture Clock Pairs in Order to Minimize Cycle-Time Overlap Violations
Patent:
7,519,927 →
Application:
12/166,561 →
Method for Hierarchical Vlsi Mask Layout Data Interrogation
Patent:
7,503,024 →
Application:
12/169,447 →
Random Initialization of Latches in an Integrated Circuit Design for Simulation
Minimizing Impact of Design Changes for Integrated Circuit Designs
Functional Verification of Power Gated Designs by Compositional Reasoning
Implementing Integrated Circuit Yield Estimation Using Voronoi Diagrams
Technique for Determining a Minimum Size of Presentation Data
Port Assignment in Hierarchical Designs by Abstracting Macro Logic
Method of Minimizing Early-Mode Violations Causing Minimum Impact to a Chip Design
Approximation of a Clock Gating Function via Bdd Path Elimination
System and Methodology for Determining Layout-Dependent Effects in Ulsi Simulation
Parallel Intrusion Search in Hierarchical Vlsi Designs with Substituting Scan Line
Hierarchy Reassembler for 1XN Vlsi Design
Closed-Loop 1XN Vlsi Design System
Compiler for Closed-Loop 1XN Vlsi Design
Integrated Design for Manufacturing for 1XN Vlsi Design
Top Level Hierarchy Wiring via 1XN Compiler
Automatically Creating Manufacturing Test Rules Pertaining to an Electronic Component
System and Method for Power Reduction Through Power Aware Latch Weighting of Complex Sub-Circuits
System and Method for Power Reduction Through Power Aware Latch Weighting
Method to Graphically Identify Registers with Unbalanced Slack as Part of Placement Driven Synthesis Optimization
Method for Bounded Transactional Timing Analysis
Gridded-Router Based Wiring on a Non-Gridded Library
Method and Apparatus for Efficient Incremental Statistical Timing Analysis and Optimization
Implementing Diagnosis of Transitional Scan Chain Defects Using Logic Built in Self Test (Lbist ) Test Patterns.
Implementing Isolation of Vlsi Scan Chain Using Abist Test Patterns
Verification of Array Built-in Self-Test (Abist) Design-for-Test/Design-for-Diagnostics (Dft/Dfd)
Electrically-Driven Optical Proximity Correction to Compensate for Non-Optical Effects
Determining Manufacturability of Lithographic Mask by Reducing Target Edge Pairs Used in Determining a Manufacturing Penalty of the Lithographic Mask
Determining Manufacturability of Lithographic Mask by Selecting Target Edge Pairs Used in Determining a Manufacturing Penalty of the Lithographic Mask
Determining Manufacturability of Lithographic Mask Using Continuous Derivatives Characterizing the Manufacturability on a Continuous Scale
Selective Compilation of a Simulation Model in View of Unavailable Higher Level Signals
Method and Apparatus for Covering a Multilayer Process Space During at-Speed Testing
Structure for Detecting Clock Gating Opportunities in a Pipelined Electronic Circuit Design
Efficient Isotropic Modeling Approach to Incorporate Electromagnetic Effects into Lithographic Process Simulations
Fast and Accurate Method to Simulate Intermediate Range Flare Effects
Method and System for Efficient Validation of Clock Skews During Hierarchical Static Timing Analysis
Scan Chain Fail Diagnostics
Method of Performing Timing Analysis on Integrated Circuit Chips with Consideration of Process Variations
Method for Efficiently Checkpointing and Restarting Static Timing Analysis of an Integrated Circuit Chip
System for Quickly Specifying Formal Verification Environments
Minterm Tracing and Reporting
Automated Use of Uninterpreted Functions in Sequential Equivalence
Method and System for Point-to-Point Fast Delay Estimation for Vlsi Circuits
Method and System for Sequential Netlist Reduction Through Trace-Containment
Techniques for Parallel Buffer Insertion
Method, System and Application for Sequential Cofactor-Based Analysis of Netlists
Effective Gate Length Circuit Modeling Based on Concurrent Length and Mobility Analysis
Enhancing Formal Design Verification by Reusing Previous Results
Improved Object Placement in Integrated Circuit Design
Integrated Circuit Modeling Based on Empirical Test Data
Accurate Approximation of Resistance in a Wire with Irregular Biasing and Determination of Interconnect Capacitances in Vlsi Layouts in the Presence of Catastrophic Optical Proximity Correction
Trace Containment Detection of Combinational Designs via Constraint-Based Uncorrelated Equivalence Checking
Method and System for Selective Stress Enablement in Simulation Modeling
Method of Employing Slew Dependent Pin Capacitances to Capture Interconnect Parasitics During Timing Abstraction of Vlsi Circuits
Method for Forming Arbitrary Lithographic Wavefronts Using Standard Mask Technology
High Contrast Lithographic Masks
Chip Design and Fabrication Method Optimized for Profit
Order Independent Method of Performing Statistical N-Way Maximum/Minimum Operation for Non-Gaussian and Non-Linear Distributions
Device History Based Delay Variation Adjustment During Static Timing Analysis
Clock Gating Using Abstraction Refinement
System and Method for Common History Pessimism Relief During Static Timing Analysis
Timing Closure on Multiple Selective Corners in a Single Statistical Timing Run
Avoiding Race Conditions at Clock Domain Crossings in an Edge Based Scan Design
Method and System to at Least Partially Isolate Nets
Techniques for Performing Conditional Sequential Equivalence Checking of an Integrated Circuit Logic Design
Geometry Based Electrical Hotspot Detection in Integrated Circuit Layouts
Simultaneous Photolithographic Mask and Target Optimization
Automated Sensitivity Definition and Calibration for Design for Manufacturing Tools
Reduction of Logic and Delay Through Latch Polarity Inversion
Enhanced Analysis of Array-Based Netlists via Reparameterization
Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking Within Designs Including Memory Arrays
Array Concatenation in an Integrated Circuit Design
System and Method of Predicting Problematic Areas for Lithography in a Circuit Design
Compact Model Methodology for Pc Landing Pad Lithographic Rounding Impact on Device Performance
Method for Testing Integrated Circuits
Effective Gate Length Circuit Modeling Based on Concurrent Length and Mobility Analysis
Methods and System for Analysis and Management of Parametric Yield
Reliability Evaluation and System Fail Warning Methods Using on Chip Parametric Monitors
Compiler for Closed-Loop 1XN Vlsi Design
Compiler for Closed-Loop 1XN Vlsi Design
Methods and System for Analysis and Management of Parametric Yield
System and Method of Predicting Problematic Areas for Lithography in a Circuit Design
Related Assignments
(19)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 8, 2002
From: BROUSSARD, SCOTT J.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 012494/0253 →
Assignment of Assignor's Interest
Apr 27, 2007
From: FOREMAN, ERIC A; GRISE, GARY D; HABITZ, PETER A; IYENGAR, VIKRAM
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 019222/0311 →
Assignment of Assignor's Interest
Jul 4, 2007
From: ARBEL, ELI; EISNER, CYNTHIA RAE; ITSKOVITCH, ALEXANDER; MAEDING, NICOLAS
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 019515/0747 →
Assignment of Assignor's Interest
Jul 17, 2007
From: MELVILLE, DAVID O.S.; ROSENBLUTH, ALAN E.; TIAN, KEHAN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 019572/0598 →
Assignment of Assignor's Interest
Jul 18, 2007
From: BAG, SANDIP; CHOUDHURY, SHUBHODEEP ROY; DUSANAPUDI, MANOJ; HATTI, SUNIL SURESH
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 019570/0202 →
Assignment of Assignor's Interest
Jul 18, 2007
From: BUSSA, VINOD; DUSANAPUDI, MANOJ; HATTI, SUNIL SURESH; KAPOOR, SHAKTI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 019570/0380 →
Assignment of Assignor's Interest
Jul 26, 2007
From: LU, NING
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 019610/0739 →
Assignment of Assignor's Interest
Jul 27, 2007
From: DOURIET, DANIEL; HARIDASS, ANAND; HUBER, ANDREAS; WEEKLY, ROGER D.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 019615/0747 →
Assignment of Assignor's Interest
Jul 31, 2007
From: DENNIS, RICK L.; HWANG, CHARLIE C.; NEVES, JOSE L.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 019623/0537 →
Assignment of Assignor's Interest
Aug 9, 2007
From: BEHM, MICHAEL L.; FARAGO, STEVEN R.; HUNT, BRYAN R.; MCCANTS, STEPHEN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 019672/0161 →
Assignment of Assignor's Interest
Aug 21, 2007
From: BELL, ROBERT H., JR.; CHEN, WEN-TZER THOMAS; SESHADRI, PATTABI R.; WELLMAN, JOHN-DAVID
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 019723/0134 →
Assignment of Assignor's Interest
Aug 21, 2007
From: FERNSLER, MATTHEW EARL; JACOBSON, HANS MIKAEL; SROUJI, JOHNY; SWANSON, TODD
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 019724/0546 →
Assignment of Assignor's Interest
Aug 28, 2007
From: GERNHOEFER, VEIT; GRAY, MICHAEL S.; HIBBELER, JASON D.; WALKER, ROBERT F.
To: INTERNATIONAL BUSINESSS MACHINES CORPORATION
Reel/Frame 019756/0421 →
Assignment of Assignor's Interest
Sep 18, 2007
From: CURTIN, JAMES J.; DOUGHERTY, WILLIAM E., JR.; NEVES, JOSE L.; SEARCH, DOUGLAS S.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 019840/0432 →
Assignment of Assignor's Interest
Nov 6, 2007
From: EISNER, CYNTHIA RAE; KEIDAR-BARNER, SHARON; RUAH, SITVANIT; SHACHAM, OHAD
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020069/0823 →
Assignment of Assignor's Interest
Nov 7, 2007
From: LADIN, KARL L.; STROM, JAMES D.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020081/0546 →
Assignment of Assignor's Interest
Nov 12, 2007
From: ACAR, EMRAH; QIAN, HAIFENG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020094/0681 →
Merger and Change of Name
Jun 16, 2021
From: MENTOR GRAPHICS CORPORATION; SIEMENS INDUSTRY SOFTWARE INC.
To: SIEMENS INDUSTRY SOFTWARE INC.
Reel/Frame 056597/0234 →
Merger and Change of Name
Jun 16, 2021
From: MENTOR GRAPHICS CORPORATION; SIEMENS INDUSTRY SOFTWARE INC.
To: SIEMENS INDUSTRY SOFTWARE INC.
Reel/Frame 057279/0707 →