Method and apparatus for performing logic built-in self-testing of an integrated circuit
View Patent ↗A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.
1. A method for performing a logic built-in self-test (LBIST) on an integrated circuit, said method comprising:
performing a flush and scan test on an integrated circuit having functional combinational logic and a plurality of scan chains selectively driven by design-for-test logic for supporting LBIST, to determine whether or not each of said plurality of scan chains functions correctly;
in response to a determination that one of said plurality of scan chains does not function correctly, terminating said LBIST;
in response to a determination that each of said plurality of scan chains functions correctly, performing a structural test on said design-for-test logic to determine whether or not said design-for-test logic functions correctly;
in response to a determination that said design-for-test logic does not function correctly, terminating said LBIST;
in response to a determination that said design-for-test logic functions correctly, performing a level sensitive scan design (LSSD) test on said functional combinational logic using said design-for-test logic to determine whether or not said integrated circuit functions correctly.
2. The method of claim 1 , wherein said structural test includes testing said design-for-test logic for stuck-at-one faults.
3. The method of claim 1 , wherein said structural test includes testing said design-for-test logic for stuck-at-zero faults.
4. The method of claim 1 , wherein said structural test includes testing said design-for-test logic for slow-to-rise faults.
5. The method of claim 1 , wherein said structural test includes testing said design-for-test logic for slow-to-fall faults.
6. A method for performing a logic built-in self-test (LBIST) on an integrated circuit, said method comprising:
performing a flush and scan test on an integrated circuit having functional combinational logic and a plurality of scan chains selectively driven by design-for-test logic for supporting LBIST, to determine whether or not each of said plurality of scan chains functions correctly;
in response to a determination that one of said plurality of scan chains does not function correctly, terminating said LBIST;
in response to a determination that each of said plurality of scan chains functions correctly, performing a structural test on said design-for-test logic to determine whether or not said design-for-test logic functions correctly;
in response to a determination that said design-for-test logic does not function correctly,
disabling said design-for-test logic;
enabling redundant design-for-test logic;
performing a structural test on said redundant design-for-test logic to determine whether or not said redundant design-for-test logic functions correctly;
in response to a determination that said redundant design-for-test logic does not function correctly, terminating said LBIST;
in response to a determination that said redundant design-for-test logic functions correctly, performing a level sensitive scan design (LSSD) test on said functional combinational logic using said redundant design-for-test logic to determine whether or not said integrated circuit functions correctly; and
in response to a determination that said design-for-test logic functions correctly, performing a level sensitive scan design (LSSD) test on said functional combinational logic using said design-for-test logic to determine if said integrated circuit functions correctly.
7. The method of claim 6 , wherein said structural test includes testing said design-for-test logic for stuck-at-one faults.
8. The method of claim 6 , wherein said structural test includes testing said design-for-test logic for stuck-at-zero faults.
9. The method of claim 6 , wherein said structural test includes testing said design-for-test logic for slow-to-rise faults.
10. The method of claim 6 , wherein said structural test includes testing said design-for-test logic for slow-to-fall faults.
11. A computer-readable medium having a computer program product for performing a logic built-in self-test (LBIST) on an integrated circuit, said computer-readable medium comprising:
instructions for performing a flush and scan test on an integrated circuit having functional combinational logic and a plurality of scan chains selectively driven by design-for-test logic for supporting LBIST, to determine whether or not each of said plurality of scan chains functions correctly;
instructions for, responsive to a determination that one of said plurality of scan chains does not function correctly, terminating said LBIST;
instructions for, responsive to a determination that each of said plurality of scan chains functions correctly, performing a structural test on said design-for-test logic to determine whether or not said design-for-test logic functions correctly;
instructions for, responsive to a determination that said design-for-test logic does not function correctly, terminating said LBIST; and
instructions for, responsive to a determination that said design-for-test logic functions correctly, performing a level sensitive scan design (LSSD) test on said functional combinational logic using said design-for-test logic to determine whether or not said integrated circuit functions correctly.
12. The computer-readable medium of claim 11 , wherein said structural test includes testing said design-for-test logic for stuck-at-one faults.
13. The computer-readable medium of claim 11 , wherein said structural test includes testing said design-for-test logic for stuck-at-zero faults.
14. The computer-readable medium of claim 11 , wherein said structural test includes testing said design-for-test logic for slow-to-rise faults.
15. The computer-readable medium of claim 11 , wherein said structural test includes testing said design-for-test logic for slow-to-fall faults.