Patent Assignment
Reel/Frame 057261/0545
Merger and Change of Name
Recorded: 2021-06-18
Pages: 7
Assignors
MENTOR GRAPHICS CORPORATION
Executed: 2020-12-30
SIEMENS INDUSTRY SOFTWARE INC.
Executed: 2020-12-30
Assignee
SIEMENS INDUSTRY SOFTWARE INC.
5800 GRANITE PARKWAY, SUITE 600, PLANO, TEXAS, 75024
Covered Properties
(98)
Ca Resistance Variability Prediction Methodology
Method and Apparatus for Evaluating Integrated Circuit Design Performance Using Enhanced Basic Block Vectors That Include Data Dependent Information
System and Method for Improved Hierarchical Analysis of Electronic Circuits
Method and Apparatus for Computing Test Margins for at-Speed Testing
Rendering a Mask Using Coarse Mask Representation
Placement Driven Routing
Auto-Router Performing Simultaneous Placement of Signal and Return Paths
Multiple Voltage Threshold Timing Analysis for a Digital Integrated Circuit
Techniques for Modeling Variables in Subprograms of Hardware Description Language Programs
Method and Apparatus for Evaluating Integrated Circuit Design Model Performance Using Basic Block Vectors and Fly-by Vectors Including Microarchitecture Dependent Information
Modeling Spatial Correlations
Methods for Distributing a Random Variable Using Statistically-Correct Spatial Interpolation
Automated System and Processing for Expedient Diagnosis of Broken Shift Registers Latch Chains
Cmos Circuit Leakage Current Calculator
Method for Simplifying Tie Net Modeling for Router Performance
Generating Test Coverage Bin Based on Simulation Result
Systems and Methods Involving Designing Shielding Profiles for Integrated Circuits
Patent:
7,409,662 →
Application:
12/033,668 →
Signal Phase Verification for Systems Incorporating Two Synchronous Clock Domains
Wire Structures Minimizing Coupling Effects Between Wires in a Bus
Arbitrary Waveform Propagation Through a Logic Gate Using Timing Analysis Results
Method to Identify Timing Violations Outside of Manufacturing Specification Limits
Method for Testing Integrated Circuits
Identifying Sequential Functional Paths for Ic Testing Methods and System
Method and Apparatus for Improving Random Pattern Testing of Logic Structures
Methods for Conserving Memory in Statistical Static Timing Analysis
Method and System for Achieving Power Optimization in a Hierarchical Netlist
Methods for Practical Worst Test Definition and Debug During Block Based Statistical Static Timing Analysis
System and Method for Automated Analysis and Hierarchical Graphical Presentation of Application Results
Patent:
7,523,433 →
Application:
12/059,703 →
Techniques for Logic Built-in Self-Test Diagnostics of Integrated Circuit Devices
Method and System for Concurrent Buffering and Layer Assignment in Integrated Circuit Layout
Methods for Designing a Product Chip a Priori for Design Subsetting, Feature Analysis, and Yield Learning
Methods for Identifying Failing Timing Requirements in a Digital Design
Intersect Area Based Ground Rule for Semiconductor Design
Simultaneous Parameter-Driven and Deterministic Simulation with or Without Synchronization
Legalization of Vlsi Circuit Placement with Blockages Using Hierarchical Row Slicing
Data Correcting Hierarchical Integrated Circuit Layout Accommodating Compensate for Long Range Critical Dimension Variation
Apparatus and Method for Improved Test Controllability and Observability of Random Resistant Logic
Method of Circuit Power Tuning Through Post-Process Flattening
Method and Apparatus for Statistical Path Selection for at-Speed Testing
Method and Apparatus for Integrated Circuit Design Model Performance Evaluation Using Basic Block Vector Clustering and Fly-by Vector Clustering
Efficient Method for Locating a Short Circuit
Patent:
7,503,023 →
Application:
12/112,529 →
Test Case Generation with Backward Propagation of Predefined Results and Operand Dependencies
Method of Laying Out Integrated Circuit Design Based on Known Polysilicon Perimeter Densities of Individual Cells
Integrated Circuit with Uniform Polysilicon Perimeter Density, Method and Design Structure
Methods for Statistical Slew Propagation During Block-Based Statistical Static Timing Analysis
Method and System for Electromigration Analysis on Signal Wiring
System and Method for Auto-Routing Jog Elimination
Patent:
7,530,041 →
Application:
12/124,119 →
System and Method for Auto-Routing Jog Elimination
Patent:
7,530,042 →
Application:
12/124,120 →
Concurrently Modeling Delays Between Points in Static Timing Analysis Operation
Incremental Speculative Merging
Method and System for Formal Verification of an Electronic Circuit Design
Method and Apparatus for Performing Logic Built-in Self-Testing of an Integrated Circuit
Method and System for Implementing Pattern Matching of Integrated Circuit Features Using Voronoi Diagrams
Methods, Systems and Computer Program Products for Layout Device Matching Driven by a Schematic Editor
Techniques for Performing a Logic Built-in Self-Test in an Integrated Circuit Device
Wiring Methods to Reduce Metal Variation Effects on Launch-Capture Clock Pairs in Order to Minimize Cycle-Time Overlap Violations
Patent:
7,519,927 →
Application:
12/166,561 →
Method for Hierarchical Vlsi Mask Layout Data Interrogation
Patent:
7,503,024 →
Application:
12/169,447 →
Functional Verification of Power Gated Designs by Compositional Reasoning
Implementing Integrated Circuit Yield Estimation Using Voronoi Diagrams
Port Assignment in Hierarchical Designs by Abstracting Macro Logic
Approximation of a Clock Gating Function via Bdd Path Elimination
Hierarchy Reassembler for 1XN Vlsi Design
Closed-Loop 1XN Vlsi Design System
Compiler for Closed-Loop 1XN Vlsi Design
Integrated Design for Manufacturing for 1XN Vlsi Design
Top Level Hierarchy Wiring via 1XN Compiler
System and Method for Power Reduction Through Power Aware Latch Weighting of Complex Sub-Circuits
Method to Graphically Identify Registers with Unbalanced Slack as Part of Placement Driven Synthesis Optimization
Method for Bounded Transactional Timing Analysis
Method and Apparatus for Efficient Incremental Statistical Timing Analysis and Optimization
Implementing Diagnosis of Transitional Scan Chain Defects Using Logic Built in Self Test (Lbist ) Test Patterns.
System, Method, and Computer Program Product for Determining Equivalence of Netlists Utilizing at Least One Transformation
Patent:
8,122,401 →
Application:
12/260,837 →
System, Method, and Computer Program Product for Determining Equivalence of Netlists Utilizing Abstractions and Transformations
Patent:
8,117,571 →
Application:
12/260,851 →
Verification of Array Built-in Self-Test (Abist) Design-for-Test/Design-for-Diagnostics (Dft/Dfd)
Electrically-Driven Optical Proximity Correction to Compensate for Non-Optical Effects
Selective Compilation of a Simulation Model in View of Unavailable Higher Level Signals
Structure for Detecting Clock Gating Opportunities in a Pipelined Electronic Circuit Design
Efficient Isotropic Modeling Approach to Incorporate Electromagnetic Effects into Lithographic Process Simulations
Method for Efficiently Checkpointing and Restarting Static Timing Analysis of an Integrated Circuit Chip
Verification Test Failure Analysis
Method and System for Point-to-Point Fast Delay Estimation for Vlsi Circuits
Generating Worst Case Test Sequences For Non-Linearly Driven Channels
Synthesis Using Multiple Synthesis Engine Configurations
Method and System for Sequential Netlist Reduction Through Trace-Containment
Method, System and Application for Sequential Cofactor-Based Analysis of Netlists
Improved Object Placement in Integrated Circuit Design
Integrated Circuit Modeling Based on Empirical Test Data
Trace Containment Detection of Combinational Designs via Constraint-Based Uncorrelated Equivalence Checking
Method and System for Selective Stress Enablement in Simulation Modeling
Method of Employing Slew Dependent Pin Capacitances to Capture Interconnect Parasitics During Timing Abstraction of Vlsi Circuits
Method for Forming Arbitrary Lithographic Wavefronts Using Standard Mask Technology
High Contrast Lithographic Masks
Chip Design and Fabrication Method Optimized for Profit
Order Independent Method of Performing Statistical N-Way Maximum/Minimum Operation for Non-Gaussian and Non-Linear Distributions
Device History Based Delay Variation Adjustment During Static Timing Analysis
Trace Routing According To Freeform Sketches
Geometry Based Electrical Hotspot Detection in Integrated Circuit Layouts
Delta Retiming in Logic Simulation
Related Assignments
(18)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 3, 2008
From: CHIDAMBARRAO, DURESETI; HENG, FOOK-LUEN; LAVIN, MARK A.; LEE, JIN-FUW
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020312/0864 →
Assignment of Assignor's Interest
Jan 11, 2008
From: BELL, ROBERT H.; CHEN, THOMAS W.; EICKEMEYER, RICHARD J.; INDUKURU, VENKAT R.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020354/0145 →
Assignment of Assignor's Interest
Jan 11, 2008
From: SHEPHARD, III., PHILIP G.; LEDALLA, RAVICHANDER; RAO, VASANT; SOREFF, JEFFREY P.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020355/0354 →
Assignment of Assignor's Interest
Jan 22, 2008
From: VISWESWARIAH, CHANDRAMOULI; XIONG, JINJUN; ZOLOTOV, VLADIMIR
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020394/0935 →
Assignment of Assignor's Interest
Jan 23, 2008
From: LAVIN, MARK A.; MUKHERJEE, MAHARAJ; ROSENBLUTH, ALAN E.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020401/0764 →
Assignment of Assignor's Interest
Jan 23, 2008
From: YIFRACH, SHAUL; BAR-JOSHUA, MICHAEL; TSACHI, ITAMAR; YEGER, BOAZ
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020402/0129 →
Assignment of Assignor's Interest
Jan 29, 2008
From: CHRISTO, MICHAEL A.; MALDONADO, JULIO A.; WEEKLY, ROGER D.; ZHOU, TINGDONG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020428/0526 →
Assignment of Assignor's Interest
Jan 30, 2008
From: ABBASPOUR, SOROUSH; FELDMANN, PETER
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020435/0564 →
Assignment of Assignor's Interest
Jan 30, 2008
From: DRASNY, GABOR; EL-ZEIN, ALI S.; ROESNER, WOLFGANG; ZARAKET, FADI A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020437/0833 →
Assignment of Assignor's Interest
Feb 5, 2008
From: BELL, ROBERT H.; CHEN, THOMAS W.; INDUKURU, VENKAT R.; SESHADRI, PATTABI M.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020466/0540 →
Assignment of Assignor's Interest
Feb 11, 2008
From: LU, NING
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020486/0877 →
Assignment of Assignor's Interest
Feb 13, 2008
From: KUMAR, MUKESH; HEMMETT, JEFFREY G.; WOODS, WAYNE H., JR.; ZEMKE, COLE E.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020504/0583 →
Assignment of Assignor's Interest
Feb 16, 2008
From: ECKELMAN, JOSEPH; FORLENZA, DONATO O; FORLENZA, ORAZIO P.; GASS, ROBERT B.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020520/0891 →
Assignment of Assignor's Interest
Feb 18, 2008
From: BERRY, CHRISTOPHER J.; BOWEN, MICHAEL ALEXANDER
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020522/0176 →
Assignment of Assignor's Interest
Feb 18, 2008
From: CORREALE, ANTHONY, JR; ROHATGI, NISHITH; BOWERS, BENJAMIN JOHN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020521/0560 →
Assignment of Assignor's Interest
Feb 19, 2008
From: DITMYER, BRUCE J.; BUETI, SUSAN FARMER; EBBERS, JONATHAN P.; GRANATO, SUZANNE
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020526/0571 →
Assignment of Assignor's Interest
Feb 20, 2008
From: LADIN, KARL L.; UNTERBORN, ERIK S.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020531/0375 →
Assignment of Assignor's Interest
Feb 1, 2013
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 029733/0156 →