Top level hierarchy wiring via 1×N compiler

1. A method, comprising:

using a computer to perform the following operations:

determining higher-level coordinates for a blockage of a 1×N building block, wherein the blockage is from higher-level wiring for an area above the 1×N building block;

determining intra-1×N coordinates for the blockage via the higher-level coordinates; and

creating routes of intra-1×N wires of the 1×N building block that avoid the intra-1×N coordinates.

2. The method of claim 1 , further comprising using the computer to perform the operation of storing the intra-1×N coordinates in an image file for a routing tool of an integrated circuit (IC) design application.

3. The method of claim 2 , further comprising using the computer to perform the operation of recompiling, via the image file, the 1×N building block to create one of a behavioral representation, a logical representation, and a physical design representation.

4. The method of claim 2 , further comprising using the computer to perform the operation of creating additional routes of intra-1×N wires based on the recompiling of the 1×N building block.

5. The method of claim 2 , wherein the using the computer to perform the operation of creating the routes comprises using the computer to perform the operation of reading the image file for a routing tool of an IC design application.

6. The method of claim 1 , further comprising using the computer to perform the operation of adding the 1×N building block to a list that comprises 1×N building blocks with blockages, wherein the list is to be used for using the computer to perform the operation of creating routes of intra-1×N wires for the 1×N building blocks.

7. The method of claim 1 , wherein the using the computer to perform the operation of determining the higher-level coordinates for the blockage comprises using the computer to perform the operation of interpreting physical information for at least one of global wiring metal and a via.

8. An apparatus, comprising:

a higher-level wiring examiner to examine higher-level wiring of an area near a 1×N building block of a physical design representation;

a blockage determiner to determine a blockage via the examination, wherein the blockage affects intra-1×N wiring for the 1×N building block; and

a coordinate calculator to calculate coordinates of the blockage, wherein the calculated coordinates enable a routing tool to avoid the blockage when creating intra-1×N wiring for the 1×N building block.

9. The apparatus of claim 8 , further comprising a placement generator to generate a physical placement for the 1×N building block in the physical design representation.

10. The apparatus of claim 9 , wherein the higher-level wiring examiner, the blockage determiner, and the coordinate calculator comprise elements of a 1×N compiler, wherein the 1×N compiler is arranged to generate updated behavioral representations, updated logical representations, and updated physical design representations via the physical placement.

11. The apparatus of claim 8 , further comprising an intra-1×N router to generate intra-1×N wire routing and vias for the 1×N building block.

12. The apparatus of claim 8 , wherein the apparatus is arranged to save a shape of the calculated coordinates in an image file to be used by the routing tool.

13. The apparatus of claim 8 , further comprising the routing tool.

14. The apparatus of claim 8 , wherein the higher-level wiring examiner is arranged to examine areas near a plurality of 1×N building blocks of a list, wherein the list comprises a subset of 1×N building blocks of the physical design representation.

15. A computer program product comprising:

one or more computer-readable, tangible storage devices;

program instructions, stored on at least one of the one or more storage devices, to determine higher-level coordinates for a blockage of a 1×N building block, wherein the blockage is from higher-level wiring for an area above the 1×N building block;

program instructions, stored on at least one of the one or more storage devices, to determine intra-1×N coordinates for the blockage via the higher-level coordinates; and

program instructions, stored on at least one of the one or more storage devices, to create routes of intra-1×N wires of the 1×N building block that avoid the intra-1×N coordinates.

16. The computer program product of claim 15 , further comprising program instructions, stored on at least one of the one or more storage devices, to store the intra-1×N coordinates in an image file for use with a routing tool.

17. The computer program product of claim 16 , further comprising program instructions, stored on at least one of the one or more storage devices, to recompile the 1×N building block, via the image file, and create updated behavioral representations, updated logical representations, and updated physical design representations.

18. The computer program product of claim 17 , further comprising program instructions, stored on at least one of the one or more storage devices, to create additional routes of intra-1×N wires based on the recompilation.

19. The computer program product of claim 16 , further comprising program instructions, stored on at least one of the one or more storage devices, to read the image file for the routing tool.

20. The computer program product of claim 15 , wherein the program instructions that determine the intra-1×N coordinates determine the intra-1×N coordinates based on higher-level wiring that causes one of a short and a design rule check violation.