Hierarchy reassembler for 1×N VLSI design

1. A computer-implemented method, comprising:

creating a flat netlist from a first hierarchical representation of a 1×N building block, wherein the flat netlist comprises attributes created via a 1×N compiler and the attributes describe hierarchical information of the 1×N building block;

altering an element of the flat netlist via at least one of a logic design tool, a synthesis tool, a physical design tool, and a timing analysis tool;

detecting the alteration of the element by comparing a first version of the flat netlist before the alteration with a second version of the flat netlist after the alteration; and

generating via the attributes, a second hierarchical representation of the 1×N building block, wherein the second representation reflects the altering of the element using a processor.

2. The method of claim 1 , wherein the generating the second hierarchical representation comprises applying the altering of the element to at least one of a hierarchical register transfer level (RTL) netlist and a physical design netlist.

3. The method of claim 1 , further comprising comparing the flat netlist to a build list of the 1×N building block to generate the second hierarchical representation.

4. The method of claim 1 , further comprising detecting deletion of a second 1×N building block from the flat netlist.

5. The method of claim 1 , further comprising detecting a second 1×N building block added to the flat netlist.

6. The method of claim 1 , wherein the generating the second hierarchical representation comprises creating a second netlist for the 1×N building block, wherein further the second netlist comprises physical elements of the 1×N building block.

7. The method of claim 1 , wherein the generating the second hierarchical representation comprises generating at least one of a behavioral representation, a logical representation, and a physical design representation.

8. The method of claim 1 , wherein an attribute of the attributes comprise at least one of a hierarchical instance name, a name of the 1×N building block, a hierarchical pin name, hierarchical pin connectivity, and a mark of a second 1×N building block marked for deletion.

9. An apparatus, comprising:

a 1×N compiler to create attributes for a flat netlist, wherein the flat netlist comprises elements of a hierarchical representation of a 1×N building block, and the attributes describe hierarchical information of the 1×N building block; and

a reassembler to create, via the attributes, a second hierarchical representation that reflects an alteration of an element of the 1×N building block, wherein the alteration is of the flat netlist via at least one of a logic design tool, a synthesis tool, a physical design tool, and a timing analysis tool and the alteration is detected by comparing a first version of the flat netlist before the alteration with a second version of the flat netlist after the alteration.

10. The apparatus of claim 9 , further comprising a 1×N block builder to create the 1×N building block.

11. The apparatus of claim 9 , further comprising a back-annotator to detect the alteration via a comparison of the second hierarchical representation and to automatically update at least one of a behavioral representation, a logical representation, and a physical representation.

12. The apparatus of claim 11 , wherein the at least one of the behavioral representation, the logical representation, and the physical representation comprises a hierarchical register transfer level (RTL) netlist or a physical design netlist.

13. The apparatus of claim 9 , wherein the reassembler is arranged to create the second hierarchical representation via the flat netlist and a list of 1×N building blocks in an integrated circuit design.

14. The apparatus of claim 13 , wherein the wherein the second hierarchical representation comprises a hierarchical RTL netlist for the 1×N building block.

15. The apparatus of claim 9 , wherein the reassembler is arranged to detect deletion of a second 1×N building block from the flat netlist.

16. The apparatus of claim 9 , wherein the reassembler is arranged to detect addition of a second 1×N building block to the flat netlist.

17. The apparatus of claim 9 , wherein the 1×N compiler is arranged to generate an updated logical representation, an updated behavioral representation, and an updated physical design representation of the 1×N building block.

18. The apparatus of claim 17 , wherein the updated behavioral representation comprises a behavioral RTL text file, wherein further the updated logical representation comprises a gate-level RTL netlist, wherein further the physical design representation comprises at least one of a hierarchical physical design netlist, a partially-flattened netlist, and a fully-flattened netlist.

19. The apparatus of claim 9 , wherein the attributes comprise tags attached to the flat netlist.

20. The apparatus of claim 9 , wherein the attributes are embedded in the flat netlist.

21. A computer program product comprising:

a non-transitory computer readable storage medium including instructions that, when executed by a processor:

create attributes for a flat netlist of elements of a 1×N building block, wherein the attributes are based upon hierarchy of the 1×N building block;

detect an alteration of one of the elements by comparing a first version of the flat netlist before the alteration with a second version of the flat netlist after the alteration; and

create a hierarchical representation of the 1×N building block, wherein the hierarchical representation includes the alteration, wherein further the alteration is via at least one of a logic design tool, a synthesis tool, a physical design tool, and a timing analysis tool.

22. The computer program product of claim 21 , wherein the hierarchical representation comprises a register transfer level (RTL) netlist or a physical design netlist.