System and method for power reduction through power aware latch weighting of complex sub-circuits

1. A system embodied in a hardware system, comprising:

a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain;

wherein the circuit analysis module is further configured to identify sub-circuits within the DUT;

a don't-care analysis module coupled to the circuit analysis module and configured to identify absolute don't-care latches associated with the identified sub-circuits;

wherein the circuit analysis module is further configured to identify a logical description of an identified sub-circuit;

a sub-circuit exception module coupled to the circuit analysis module and configured to select weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit; and

wherein the sub-circuit exception module is further configured to store the selected weighted input values for the identified sub-circuit and to associate the selected weighted input values with the logical description.

2. The system of claim 1 , further comprising:

wherein the don't-care analysis module is further configured to identify conditional don't-care latches associated with the identified sub-circuits; and

wherein the sub-circuit exception module is further configured to select weighted input values for an identified sub-circuit based on the identified conditional don't-care latches and the logical description of the identified sub-circuit.

3. The system of claim 1 , further comprising:

wherein the don't-care analysis module is further configured to identify absolute don't-care bits within a general test pattern;

wherein the sub-circuit exception module is further configured to replace identified absolute don't-care bits in the general test pattern according to the stored weighted value associated with the logical description of the identified sub-circuit, to generate a weighted test pattern;

a test vector module coupled to the test pattern generator module and configured to generate a test vector based on the weighted test pattern; and

an input module configured to apply the test vector to the DUT.

4. The system of claim 1 , further comprising:

wherein the don't-care analysis module is further configured to identify conditional don't-care bits within a general test pattern;

wherein the sub-circuit exception module is further configured to replace identified conditional don't-care bits in the general test pattern according to the stored weighted value associated with the logical description of the identified sub-circuit, to generate a weighted test pattern;

a test vector module coupled to the test pattern generator module and configured to generate a test vector based on the weighted test pattern; and

an input module configured to apply the test vector to the DUT.

5. The system of claim 1 , further comprising:

a test heuristics module configured to generate test heuristics; and

a test pattern generator module coupled to the test heuristics module and configured to generate a general test pattern based on the test heuristics.

6. The system of claim 1 , wherein selecting weighted input values comprises:

comparing the logical description of the identified sub-circuit to a database of known sub-circuits, the database comprising a plurality of weights associated with each known sub-circuit;

if the identified sub-circuit is a known sub-circuit, using the weights stored in the sub-circuit exception module; and

if the identified sub-circuit is not a known sub-circuit, storing the logical description of the identified sub-circuit.

7. The system of claim 6 , wherein selecting weighted input values further comprises, in the event the identified sub-circuit is not a known sub-circuit:

weighting the input values of the identified sub-circuit with a first weight configuration;

simulating power through the identified sub-circuit in a first test;

generating a first power data based on the first weight configuration and the first test;

weighting the input values of the identified sub-circuit with a second weight configuration;

simulating power through the identified sub-circuit in a second test;

generating a second power data based on the second weight configuration and the second test;

comparing the first power data to the second power data;

selecting the weight configuration requiring lower power consumption; and

storing the selected weight configuration in the database as associated with the identified sub-circuit.

8. A method, comprising:

analyzing a device under test (DUT) to identify sub-circuits within the DUT, the DUT comprising a plurality of latches coupled together in a scan chain;

identifying absolute don't-care latches associated with the identified sub-circuits;

identifying a logical description of an identified sub-circuit;

selecting weighted input values for the identified sub-circuit, based on the identified absolute don't-care latches and the logical description;

storing the selected weighted input values for the identified sub-circuit; and

associating the selected weighted input values with the logical description of the identified sub-circuit.

9. The method of claim 8 , further comprising:

identifying conditional don't-care latches associated with the identified sub-circuits; and

selecting weighted input values for an identified sub-circuit based on the identified conditional don't-care latches and the logical description of the identified sub-circuit.

10. The method of claim 8 , further comprising:

identifying absolute don't-care bits within a general test pattern;

replacing identified absolute don't-care bits in the general test pattern according to the stored weighted value associated with the logical description of the identified sub-circuit, to generate a weighted test pattern;

generating a test vector based on the weighted test pattern; and

applying the test vector to the DUT.

11. The method of claim 8 , further comprising:

identifying conditional don't-care bits within a general test pattern;

replacing identified conditional don't-care bits in the general test pattern according to the stored weighted value associated with the logical description of the identified sub-circuit, to generate a weighted test pattern;

generating a test vector based on the weighted test pattern; and

applying the test vector to the DUT.

12. The method of claim 8 , further comprising:

generating test heuristics; and

generating a general test pattern based on the test heuristics.

13. The method of claim 8 , wherein selecting weighted input values comprises:

comparing the logical description of the identified sub-circuit to a database of known sub-circuits, the database comprising a plurality of weights associated with each known sub-circuit;

if the identified sub-circuit is a known sub-circuit, using the weights stored in the sub-circuit exception module; and

if the identified sub-circuit is not a known sub-circuit, storing the logical description of the sub-circuit.

14. The method of claim 13 , wherein selecting weighted input values further comprises, in the event the identified sub-circuit is not a known sub-circuit:

weighting the input values of the identified sub-circuit with a first weight configuration;

simulating power through the identified sub-circuit in a first test;

generating a first power data based on the first weight configuration and the first test;

weighting the input values of the identified sub-circuit with a second weight configuration;

simulating power through the identified sub-circuit in a second test;

generating a second power data based on the second weight configuration and the second test;

comparing the first power data to the second power data;

selecting the weight configuration requiring lower power consumption; and

storing the selected weight configuration in the database as associated with the identified sub-circuit.

15. A computer program product for power reduction during testing, the computer program product comprising:

a non-transitory computer usable medium having computer useable program code embodied therewith, the computer useable program code comprising:

computer usable program code configured to analyze a device under test (DUT) to identify sub-circuits within the DUT, the DUT comprising a plurality of latches coupled together in a scan chain;

computer usable program code configured to identify absolute don't-care latches associated with the identified sub-circuits;

computer usable program code configured to identify a logical description of an identified sub-circuit;

computer usable program code configured to select weighted input values for the identified sub-circuit, based on the identified absolute don't-care latches and the logical description;

computer usable program code configured to store the selected weighted input values for the identified sub-circuit; and

computer usable program code configured to associate the selected weighted input values with the logical description of the identified sub-circuit.

16. The computer program product of claim 15 , further comprising:

computer usable program code configured to identify conditional don't-care latches associated with the identified sub-circuits; and

computer usable program code configured to select weighted input values for an identified sub-circuit based on the identified conditional don't-care latches and the logical description of the identified sub-circuit.

17. The computer program product of claim 15 , further comprising:

computer usable program code configured to identify absolute don't-care bits within a general test pattern;

computer usable program code configured to replace identified absolute don't-care bits in the general test pattern according to the stored weighted value associated with the logical description of the identified sub-circuit, to generate a weighted test pattern;

computer usable program code configured to generate a test vector based on the weighted test pattern; and

computer usable program code configured to apply the test vector to the DUT.

18. The computer program product of claim 15 , further comprising:

computer usable program code configured to identify conditional don't-care bits within a general test pattern;

computer usable program code configured to replace identified conditional don't-care bits in the general test pattern according to the stored weighted value associated with the logical description of the identified sub-circuit, to generate a weighted test pattern;

computer usable program code configured to generate a test vector based on the weighted test pattern; and

computer usable program code configured to apply the test vector to the DUT.

19. The computer program product of claim 15 , wherein selecting weighted input values comprises:

comparing the logical description of the identified sub-circuit to a database of known sub-circuits, the database comprising a plurality of weights associated with each known sub-circuit;

if the identified sub-circuit is a known sub-circuit, using the weights stored in the sub-circuit exception module; and

if the identified sub-circuit is not a known sub-circuit, storing the logical description of the sub-circuit.

20. The computer program product of claim 19 , wherein selecting weighted input values further comprises, in the event the identified sub-circuit is not a known sub-circuit:

weighting the input values of the identified sub-circuit with a first weight configuration;

simulating power through the identified sub-circuit in a first test;

generating a first power data based on the first weight configuration and the first test;

weighting the input values of the identified sub-circuit with a second weight configuration;

simulating power through the identified sub-circuit in a second test;

generating a second power data based on the second weight configuration and the second test;

comparing the first power data to the second power data;

selecting the weight configuration requiring lower power consumption; and

storing the selected weight configuration in the database as associated with the identified sub-circuit.