Compiler for closed-loop 1×N VLSI design
View Patent ↗Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.
1. An apparatus, comprising:
a first generator to generate a behavioral representation of a design for an integrated circuit including 1×N arrays of cells, wherein the behavioral representation comprises a register transfer level (RTL) description of one of the 1×N arrays of cells;
a second generator to generate a logical representation of the design, wherein further the second generator is arranged to generate the logical representation via a flat netlist of a physical design representation, wherein further the flat netlist comprises a circuit element altered via at least one of a logic design tool, a synthesis tool, a physical design tool, and a timing analysis tool; and
a third generator to generate the physical design representation of the design, wherein at least one of the behavioral, logical, and physical design representations is generated by detecting the alteration of the circuit element from a comparison of the flat netlist with a second netlist of the design before the alteration.
2. The apparatus of claim 1 , further comprising a script generator to generate helper script, wherein the helper script is to enable one of the first, second, and third generators to create a second one of the 1×N arrays of cells.
3. The apparatus of claim 1 , further comprising a rule checker to check for design violations of at least one of the behavioral representation, the logical representation, and the physical design representation.
4. The apparatus of claim 3 , wherein the rule checker is arranged to check for one of capacitance violations, drive strength violations, and element placement violations.
5. The apparatus of claim 1 , wherein one of the first, second, and third generators is arranged to alter one of a view type and a hardware description language (HDL) based on the at least one of the logic design tool, the synthesis tool, the physical design tool, and the timing analysis tool.
6. The apparatus of claim 1 , wherein one of the first, second, and third generators is arranged to accept a manual change of the design and incorporate the manual change in at least one of the behavioral, logical, and physical design representations.
7. The apparatus of claim 1 , wherein one of the second and third generators is arranged to detect the alteration of the circuit element and incorporate the alteration in one of the logical representation and the physical design representation.
8. The apparatus of claim 1 , wherein the behavioral representation comprises an RTL netlist, the logical representation comprises gate-level RTL, and the physical design representation comprises a physical RTL netlist.
9. The apparatus of claim 1 , wherein the first, second, and third generators comprise a 1×N compiler.
10. The apparatus of claim 9 , wherein the 1×N compiler is arranged to determine reuse of said one of the 1×N arrays of cells via an analysis of a netlist, wherein the netlist comprises one of the behavioral representation, the logical representation, and the physical design representation.
11. The apparatus of claim 1 , wherein second generator is arranged to create attributes for the physical design representation, wherein the attributes enable the third generator preserve a hierarchical definition of said one of the 1×N arrays of cells in a flattened netlist and enable the first generator to generate the hierarchical definition in the behavioral representation.