Arbitrary waveform propagation through a logic gate using timing analysis results

1. A method, performed on a computer system, for determining an effect of noise on a digital integrated circuit having at least one logic gate, the method comprising:

using the computer system to perform the following:

performing a timing analysis on the at least one logic gate;

performing a noise analysis on the at least one logic gate;

dynamically synthesizing a waveform propagation model as a function of the timing analysis, wherein the waveform propagation model contains a representation of how noise impacts the timing analysis of the at least one logic gate, wherein the dynamically synthesizing of the waveform propagation model comprises determining a low-pass filtering effect of the at least one logic gate, and determining a non-linear element of the at least one logic gate as a function of a voltage waveform outputted from the at least one logic gate during the timing analysis and the response that the low-pass filtering effect has on a voltage waveform inputted to the at least one logic gate during the timing analysis;

applying an arbitrary voltage waveform derived from the noise analysis to the dynamically synthesized waveform propagation model; and

determining an effect of the arbitrary voltage waveform on the at least one logic gate from the dynamically synthesized waveform propagation model.

2. The method according to claim 1 , wherein the performing of a timing analysis comprises:

propagating a voltage waveform from an input of the at least one logic gate to an output of the at least one logic gate; and

determining propagation delay of the at least one logic gate as the voltage waveform propagates from the input of the at least one logic gate to the output of the at least one logic gate.

3. The method according to claim 1 , wherein the determining of the low-pass filtering effect comprises determining an RC filter representative of propagation delay of the at least one logic gate.

4. The method according to claim 3 , wherein the RC filter is determined as a function of the voltage waveform inputted to the at least one logic gate during the timing analysis and the propagation delay of the at least one logic gate.

5. The method according to claim 1 , wherein the dynamically synthesizing of the waveform propagation model comprises determining a non-linear element of the at least one logic gate that is representative of a DC transfer characteristic.

6. The method according to claim 1 , wherein the determining of the effect of the arbitrary voltage waveform comprises determining an output voltage waveform generated from the dynamically synthesized waveform propagation model for the applied arbitrary voltage waveform.

7. The method according to claim 6 , further comprising determining the effect of noise on the timing analysis of the at least one logic gate from the determined output voltage waveform.

8. The method according to claim 6 , further comprising determining the effect of noise on slew for the at least one logic gate from the determined output voltage waveform.

9. The method according to claim 6 , further comprising determining the effect of noise on delay for the at least one logic gate from the determined output voltage waveform.

10. The method according to claim 1 , wherein the applying of the arbitrary voltage waveform comprises applying a noisy waveform derived from the noise analysis and timing analysis.

11. The method according to claim 1 , wherein the applying of the arbitrary voltage waveform comprises applying a noise glitch waveform.

12. A computer-readable storage device storing computer instructions, which when executed, enables a computer system to determine an effect of noise on a digital integrated circuit having at least one logic gate, the computer instructions comprising:

performing a timing analysis on the at least one logic gate;

performing a noise analysis on the at least one logic gate;

dynamically synthesizing a waveform propagation model as a function of the timing analysis, wherein the waveform propagation model contains a representation of how noise impacts the timing analysis of the at least one logic gate, wherein the dynamically synthesizing of the waveform propagation model comprises instructions for determining an RC filter representative of propagation delay of the at least one logic gate, and determining a non-linear element of the at least one logic gate as a function of a voltage waveform outputted from the at least one logic gate during the timing analysis and the response that the RC filter has on a voltage waveform inputted to the at least one logic gate during the timing analysis;

applying an arbitrary voltage waveform derived from the noise analysis to the dynamically synthesized waveform propagation model; and

determining an effect of the arbitrary voltage waveform on the at least one logic gate from the dynamically synthesized waveform propagation model.

13. The computer-readable storage device according to claim 12 , wherein the performing of a timing analysis comprises instructions for:

propagating a voltage waveform from an input of the at least one logic gate to an output of the at least one logic gate; and

determining propagation delay of the at least one logic gate as the voltage waveform propagates from the input of the at least one logic gate to the output of the at least one logic gate.

14. The computer-readable storage device according to claim 12 , wherein the RC filter is determined as a function of the voltage waveform inputted to the at least one logic gate during the timing analysis and the propagation delay of the at least one logic gate.

15. The computer-readable storage device according to claim 12 , wherein the determining of the effect of the arbitrary voltage waveform comprises instructions for determining an output voltage waveform generated from the dynamically synthesized waveform propagation model for the applied arbitrary voltage waveform.

16. The computer-readable storage device according to claim 15 , further comprising instructions for determining noise analysis computations from the determined output voltage waveform, wherein the noise analysis computations comprise the effect of noise on the timing analysis of the at least one logic gate, the effect of noise on the slew for the at least one logic gate and the effect of noise on the delay for the at least one logic gate.

17. A computer system for determining an effect of noise on a digital integrated circuit having at least one logic gate, comprising:

at least one processing unit;

memory operably associated with the at least one processing unit; and

an arbitrary waveform propagation tool storable in memory and executable by the at least one processing unit for determining the effect of noise on the digital integrated circuit having at least one logic gate, the tool comprising:

a timing analysis component configured to perform a timing analysis on the at least one logic gate;

a noise analysis component configured to perform a noise analysis on the at least one logic gate; and

a waveform propagation model synthesizer component configured to dynamically synthesize a waveform propagation model as a function of the timing analysis, wherein the waveform propagation model contains a representation of how noise impacts the timing analysis of the at least one logic gate, wherein the waveform propagation model synthesizer component is configured to determine an RC filter representative of propagation delay of the at least one logic gate, wherein the waveform propagation model synthesizer component is configured to determine a non-linear element of the at least one logic gate as a function of a voltage waveform outputted from the at least one logic gate during the timing analysis and the response that the RC filter has on a voltage waveform inputted to the at least one logic gate during the timing analysis, wherein the waveform propagation model synthesizer component is further configured to apply an arbitrary voltage waveform comprising one of a noisy waveform or noise glitch waveform that is derived from the noise analysis to the dynamically synthesized waveform propagation model and determine an effect of the arbitrary voltage waveform on the at least one logic gate from the dynamically synthesized waveform propagation model.

18. The system according to claim 17 , wherein the timing analysis component is configured to propagate a voltage waveform from an input of the at least one logic gate to an output of the at least one logic gate and determine propagation delay of the at least one logic gate as the voltage waveform propagates from the input of the at least one logic gate to the output of the at least one logic gate.

19. The system according to claim 18 , wherein the RC filter is determined as a function of the voltage waveform inputted to the at least one logic gate during the timing analysis and the propagation delay of the at least one logic gate.

20. The system according to claim 17 , wherein the waveform propagation model synthesizer component is further configured to determine an output voltage waveform generated from the dynamically synthesized waveform propagation model for the applied noisy voltage waveform and determine noise analysis computations from the determined output voltage waveform, wherein the noise analysis computations comprise the effect of noise on the timing analysis of the at least one logic gate, the effect of noise on the slew for the at least one logic gate and the effect of noise on the delay for the at least one logic gate.