Method and system for point-to-point fast delay estimation for VLSI circuits
View Patent ↗The present disclosure is directed to a method for estimating an interconnect delay for a source-to-sink path of a net within a Very Large Scale Integration (VLSI) circuit, the source-to-sink path connecting a source and a sink in the net. The method may comprise estimating a total wire capacitance; calculating a delay contribution based on delay of the source-to-sink path and delay of a plurality of off-path sinks; and estimating the interconnect delay for the source-to-sink path based on the delay contribution.
1. A method, performed by a processor executing non-transitory computer usable program code, for estimating an interconnect delay for a source-to-sink path of a net within a Very Large Scale Integration (VLSI) circuit, the source-to-sink path connecting a source and a sink in the net, comprising:
calculating by the processer an off-path-point that represents all other off-path sinks in the net;
projecting an intersect from the off-path-point to the source-to-sink path;
estimating a total wire capacitance;
calculating a delay contribution based on delay of the source-to-sink path and delay of said all other off-path sinks; and
estimating the interconnect delay for the source-to-sink path based on the delay, wherein calculating a delay contribution based on delay of the source-to-sink path and delay of said art other off-path sinks comprises:
calculating the delay contribution according to the formula
Delay
(
S
0
,
S
i
)
=
0.5
·
R
0
·
C
0
·
(
distance
(
S
0
,
S
i
)
)
2
+
R
0
·
distance
(
S
0
,
S
i
)
·
c
(
S
i
)
+
R
0
·
project_distance
(
S
0
,
S
other
,
S
i
)
·
(
c
(
T
)
-
C
0
·
distance
(
S
0
,
S
i
)
+
∑
j
=
1
…
i
-
1
,
i
+
1
…
n
-
1
c
(
S
j
)
)
.
2. The method as claimed in claim 1 , further comprising:
computing a delay due to gate output resistance for the VLSI circuit; and
refining the estimated interconnect delay for the source-to-sink path based on the delay contribution and the delay due to gate output resistance.
3. The method as claimed in claim 1 , wherein calculating an off-path-point that represents all other off-path sinks in the net comprises:
computing a center of gravity of all other sinks.
4. The method as claimed in claim 1 , wherein calculating an off-path-point that represents all other off-path sinks in the net comprises:
calculating a weighted center of gravity utilizing at least one of uniform weighting of all other sinks or capacitance weighting of all other sinks.
5. The method as claimed in claim 1 , wherein estimating a total wire capacitance comprises:
estimating the total wire capacitance according to formula
c ( T )= C 0 ×Total Wire Length.
6. The method as claimed in claim 5 , wherein the total wire length is estimated according to formula
TWL
=
{
k
·
n
·
w
R
·
h
R
when
n
≥
4
k
·
n
·
(
w
R
·
h
R
)
when
n
<
4.
7. A method, performed by a processor executing non-transitory computer usable program code, for estimating an interconnect delay for a source-to-sink path of a net within a Very Large Scale Integration (VLSI) circuit, the source-to-sink path connecting a source and a sink in the net, comprising:
projecting a plurality of off-path sinks to the source-to-sink path;
estimating a total wire capacitance;
calculating by the processer an individual delay contribution for each one of the plurality of off-path sinks;
calculating a delay contribution based on delay of the source-to-sink path and delay of the plurality of off-path sinks;
estimating the interconnect delay for the source-to-sink path based on the delay, wherein calculating a delay contribution based on delay of the source-to-sink path and delay of said art other off-path sinks comprises:
calculating the delay contribution according to the formula
Delay
(
S
0
,
S
i
)
=
0.5
·
R
0
·
C
0
·
(
distance
(
S
0
,
S
i
)
)
2
+
R
0
·
distance
(
S
0
,
S
i
)
·
c
(
S
i
)
+
R
0
·
project_distance
(
S
0
,
S
other
,
S
i
)
·
(
c
(
T
)
-
C
0
·
distance
(
S
0
,
S
i
)
+
∑
j
=
1
…
i
-
1
,
i
+
1
…
n
-
1
c
(
S
j
)
)
.
8. The method as claimed in claim 7 , further comprising:
computing a delay due to gate output resistance for the VLSI circuit; and
refining the estimated interconnect delay for the source-to-sink path based on the delay contribution and the delay due to gate output resistance.
9. The method as claimed in claim 8 , wherein estimating a total wire capacitance comprises:
estimating the total wire capacitance according to formula
c ( T )= C 0 ×Total Wire Length.
10. The method as claimed in claim 9 , wherein the total wire length is estimated according to formula
TWL
=
{
k
·
n
·
w
R
·
h
R
when
n
≥
4
k
·
n
·
(
w
R
·
h
R
)
when
n
<
4.
11. A non-transitory computer-readable medium having computer-executable instructions for performing a method for estimating an interconnect delay for a source-to-sink path of a net within a Very Large Scale Integration (VLSI) circuit, the source-to-sink path connecting a source and a sink in the net, comprising:
estimating a total wire capacitance;
calculating a delay contribution based on delay of the source-to-sink path and delay of a plurality of off-path sinks; and
estimating the interconnect delay for the source-to-sink path based on the delay, wherein calculating a delay contribution based on delay of the source-to-sink path and delay of a plurality of off-path sinks comprises:
calculating the delay contribution according to formula
Delay
(
S
0
,
S
i
)
=
0.5
-
R
0
·
C
0
·
(
distances
(
S
0
,
S
i
)
)
2
+
R
0
·
distance
(
S
0
,
S
i
)
·
c
(
S
i
)
+
R
0
·
project_distance
(
S
0
,
S
other
,
S
i
)
·
(
c
(
T
)
-
C
0
·
distance
(
S
0
,
S
i
)
+
∑
j
=
1
…
i
-
1
,
i
+
1
…
n
-
1
c
(
S
j
)
)
.
12. The method as claimed in claim 11 , further comprising:
computing a delay due to gate output resistance for the VLSI circuit; and
refining the estimated interconnect delay for the source-to-sink path based on the delay contribution and the delay due to gate output resistance.
13. The method as claimed in claim 11 , wherein estimating a total wire capacitance comprises:
estimating the total wire capacitance according to formula
c ( T )= C 0 ×Total Wire Length.
14. The method as claimed in claim 13 , wherein the total wire length is estimated according to formula
TWL
=
{
k
·
n
·
w
R
·
h
R
when
n
≥
4
k
·
n
·
(
w
R
·
h
R
)
when
n
<
4.
15. The non-transitory computer-readable medium having computer-executable instructions for performing a method as claimed in claim 11 , wherein calculating a delay contribution based on delay of the source-to-sink path and delay of a plurality of off-path sinks comprises:
calculating an off-path-point that represents all other off-path sinks in the net;
projecting an intersect from the off-path-point to the source-to-sink path; and
calculating a delay contribution based on delay of the source-to-sink path and delay of all other off-path sinks.
16. The method as claimed in claim 15 , wherein calculating an off-path-point that represents all other off-path sinks in the net comprises:
computing a center of gravity of all other sinks.
17. The method as claimed in claim 15 , wherein calculating an off-path-point that represents all other off-path sinks in the net comprises:
calculating a weighted center of gravity utilizing at least one of uniform weighting of all other sinks or capacitance weighting of all other sinks.
18. The computer-readable medium having computer-executable instructions for performing a method as claimed in claim 11 , wherein calculating a delay contribution based on delay of the source-to-sink path and delay of a plurality of off-path sinks comprises:
projecting the plurality of off-path sinks to the source-to-sink path;
calculating an individual delay contribution for each one of the plurality of off-path sinks; and
calculating a delay contribution based on delay of the source-to-sink path and delay of the plurality of off-path sinks based on the individual delay contribution for each one of the plurality of off-path sinks.