Method and apparatus for evaluating integrated circuit design performance using enhanced basic block vectors that include data dependent information
View Patent ↗A test system or simulator includes an IC benchmark software program that executes application software on a semiconductor die IC design model. The benchmark software includes trace, simulation point, clustering and other programs. IC designers utilize the benchmark software to evaluate the performance characteristics of IC designs with customer user software applications. The benchmark software generates basic block vectors BBVs from instruction traces of application software. The benchmark software analyzes data dependent information that it appends to BBVs to create enhanced BBVs or EBBVs. The benchmark software may graph the EBBV information in a cluster diagram and selects a subset of EBBVs as a representative sample for each program phase. Benchmarking software generates a reduced application software program from the representative EBBV samples. Designers use the test system with benchmarking software to evaluate IC design model modifications by using the representative reduced application software program.
1. A method of IC design model testing, comprising:
generating, by a simulator information handling system (IHS), a basic block vector (BBV);
determining, by the simulator IHS, data dependent information related to the BBV, thus providing related data dependent information; and
generating, by the simulator IHS, an enhanced basic block vector (EBBV) that includes the BBV and the related data dependent information.
2. The method of claim 1 , wherein the data dependent information is one of memory system information and cache miss information.
3. The method of claim 1 , wherein the simulator IHS includes benchmark software that executes on a test system that includes the IC design model.
4. The method of claim 1 , further comprising weighting, by the simulator IHS, the EBBV to affect importance of the data dependent information in the EBBV.
5. The method of claim 4 , further comprising generating, by the simulator IHS, a cluster group of EBBVs.
6. The method of claim 5 , further comprising reducing, by the simulator IHS, each cluster group to at least one cluster data point to represent the cluster group, thus generating a reduced software application that includes the at least one data point.
7. The method of claim 6 , further comprising executing, by the simulator IHS, the reduced software application to provide test information.
8. The method of claim 7 further comprising altering the IC design in response to the test information.
9. A test system comprising:
a processor;
a memory store, coupled to the processor, configured to:
generate a basic block vector (BBV);
determine data dependent information related to the BBV, thus providing related data dependent information; and
generate an enhanced basic block vector (EBBV) that includes the BBV and the related data dependent information.
10. The test system of claim 9 , wherein the memory store comprises one of a system memory and a non-volatile storage.
11. The test system of claim 9 , wherein the data dependent information is one of memory system information and cache miss information.
12. The test system of claim 9 , wherein the memory store is further configured to weight the EBBV to affect importance of the data dependent information in the EBBV.
13. The test system of claim 12 , wherein the memory store is further configured to generate a cluster group of EBBVs.
14. A test system comprising:
a processor;
a memory store, coupled to the processor, configured to:
generate a basic block vector (BBV);
determine data dependent information related to the BBV, thus providing related data dependent information;
generate an enhanced basic block vector (EBBV) that includes the BBV and the related data dependent information;
weight the EBBV to affect importance of the data dependent information in the EBBV;
generate a cluster group of EBBVs; and
reduce each cluster group to at least one cluster data point to represent the cluster group, thus generating a reduced software application that includes the at least one data point.
15. The test system of claim 14 , wherein the memory store is further configured to execute the reduced software application to provide test information.
16. A computer program product stored on a non-transitory computer storage medium, comprising:
instructions that generate a basic block vector (BBV);
instructions that determine data dependent information related to the BBV, thus providing related data dependent information; and
instructions that generate an enhanced basic block vector (EBBV) that includes the BBV and the related data dependent information.
17. The computer program product of claim 16 , wherein the data dependent information is one of memory system information and cache miss information.
18. The computer program product of claim 16 , further comprising instructions for weighting the EBBV to affect importance of the data dependent information in the EBBV.
19. The computer program product of claim 18 , further comprising instructions for generating a cluster group of EBBVs.
20. The computer program product of claim 19 , further comprising instructions for reducing each cluster group to at least one cluster data point to represent the cluster group, thus generating a reduced software application that includes the at least one data point.