Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning
View Patent ↗A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset.
1. A method of designing a product chip, the method comprising:
(a) using an automated tester to identify a plurality of signal paths within a chip design that can be readily identified from chip fail data;
(b) using a software tool to remove a fraction of the signal paths that have physical design constraints to generate a subset of the signal paths;
(c) constructing a physical implementation of the signal paths in the subset with the software tool by selecting an equal number of logic paths wired on each of a plurality of adjacent pairs of a plurality of wiring levels in a back-end-of-line (BEOL) interconnect structure;
(d) identifying with the software tool one or more signal paths in the subset that are not constructed with the respective targeted physical implementation;
(e) discarding the one or more signal paths from the subset that are not constructed with the respective targeted physical implementation; and
(f) using the subset in a design of experiment (DOE) analysis with the software tool to identify yield detractors in the plurality of wiring levels of the back-end-of-line (BEOL) interconnect structure.
2. The method of claim 1 further comprising:
estimating a number of signal paths that will establish a sufficient sample size for a given yield analysis technique.
3. The method of claim 2 wherein the number of signal paths is based upon at least one of the chip design, a predicted yield, critical areas, or feature counts.
4. The method of claim 2 further comprising:
iterating steps (c), (d), and (e) until the subset is populated with the number of test paths estimated to establish the sufficient sample size.
5. The method of claim 1 wherein the physical implementation is constructed for all of the signal paths before the one or more signal paths are identified that are not constructed consistently with the respective targeted physical implementation and discarded from the subset.
6. The method of claim 1 further comprising:
documenting each of the one or more signal paths in the subset; and
documenting a feature content of each of the one or more signal paths in the subset.
7. The method of claim 1 further comprising:
modifying the chip design based on the subset.
8. The method of claim 1 wherein identifying one or more of signal paths within the chip design further comprises:
identifying a plurality of single fanout paths tested during a logic test.