Method to graphically identify registers with unbalanced slack as part of placement driven synthesis optimization
View Patent ↗A method for identifying latches in physical designs with unbalanced slack, comprising: creating a netlist describing a logical design, the logical design having a plurality of latches therein; performing a placement of the logical design to obtain a physical design; measuring a slack difference of each of the plurality of latches; selecting a color for each of the plurality of latches based on the slack difference correspondingly measured for each of the plurality of latches; and generating a graphical image identifying each one of the plurality of latches with slack difference in color, the color selected for each one of the plurality of latches with slack difference being indicative of the severity of the slack difference.
1. A system for identifying latches in physical designs with unbalanced slack, comprising:
a placement driven synthesis (PDS) module configured to receive a netlist describing a logical design having a plurality of latches therein, the PDS module performs a placement of the logical design to obtain a physical design;
a PDS graphical system in communication with the PDS module, the PDS graphical system measures a slack difference of each of the plurality of latches and selects a color for each of the plurality of latches based on the slack difference correspondingly measured for each of the plurality of latches; and
a graphics application program interface (API) module in communication with the PDS graphical system, the graphics API module generates a graphical image identifying each one of the plurality of latches with slack difference in color, the color selected for each one of the plurality of latches with slack difference being indicative of the severity of the slack difference.
2. The system as in claim 1 , wherein the color selected for each one of the plurality of latches with slack difference differentiates between latches with greater input slack and latches with greater output slack, the color for latches with greater input slack is selected from a first range of colors while the color for latches with greater output slack is selected from a second range of colors.
3. The system as in claim 1 , wherein the graphical image plots each one of the plurality of latches with slack difference according to the placement location of each of the plurality of latches on the integrated circuit.
4. The system as in claim 1 , wherein the graphical image is generated concurrent with the performance of the placement driven synthesis.
5. The system as in claim 1 , wherein an absolute difference of the slack difference of each of the plurality of latches is calculated and normalized by design cycle time before the color for each one of the plurality of latches with slack difference is selected.
6. The system as in claim 1 , wherein a raw difference of the slack difference of each of the plurality of latches is calculated and normalized by design cycle time before the color for each one of the plurality of latches with slack difference is selected.