Methods for practical worst test definition and debug during block based statistical static timing analysis
View Patent ↗Methods for analyzing timing of an integrated circuit using block-based static statistical timing analysis and for practical worst test definition and debug. The method includes building a timing graph, determining a slack for each of the nodes in the timing graph, and identifying a statistically worst slack for at least one of the nodes. The method further includes replacing this statistically worst slack with a proxy worst slack.
1. A method for analyzing timing of an integrated circuit using a static statistical timing analysis (SSTA) tool, the method comprising:
computing a timing graph from a netlist using the SSTA tool, the timing graph having a plurality of nodes and a plurality of edges connecting the nodes;
in response to forward propagating a first set of probabilistic distributions in the timing graph, statistically calculating with the SSTA tool an arrival time of the first set of probabilistic distributions at each of the nodes;
in response to backward propagating a second set of probabilistic distributions in the timing graph, statistically calculating with the SSTA tool a required arrival time of the second set of probabilistic distributions at each of the nodes;
identifying with the SSTA tool a statistically worst slack for a node in the timing graph from the arrival times and the required arrival times either through a slack calculation based upon the arrival times and the required arrival times or through required arrival time calculations;
determining one or more of the slacks of the edges arriving at the node in the timing graph with a parameter sensitivity that exceeds a user-defined limit;
equating a proxy worst slack to the slack of the edge that produces a worst projected slack: and
generating a timing report with the SSTA tool that replaces the statistically worst slack with the proxy worst slack for at least one of the edges arriving at the node in the timing graph at which the statistically worst slack is identified during backward propagation.
2. A method for analyzing timing of an integrated circuit using a static statistical timing analysis (SSTA) tool, the method comprising:
computing a timing graph from a netlist using the SSTA tool, the timing graph having a plurality of nodes and a plurality of edges connecting the nodes;
in response to forward propagating a first set of probabilistic distributions in the timing graph, statistically calculating with the SSTA tool an arrival time of the first set of probabilistic distributions at each of the nodes;
in response to backward propagating a second set of probabilistic distributions in the timing graph, statistically calculating with the SSTA tool a required arrival time of the second set of probabilistic distributions at each of the nodes;
identifying with the SSTA tool a statistically worst slack for a node in the timing graph from the arrival times and the required arrival times either through a slack calculation based upon the arrival times and the required arrival times or through required arrival time calculations;
calculating a tightness probability for each of the edges;
comparing the tightness probabilities to identify a largest tightness probability;
equating a proxy worst slack to the slack for the edge exhibiting the largest tightness probability; and
generating a timing report with the SSTA tool that replaces the statistically worst slack with the proxy worst slack for at least one of the edges arriving at the node in the timing graph at which the statistically worst slack is identified during backward propagation.