Method, system and application for sequential cofactor-based analysis of netlists
View Patent ↗Methods, systems and computer products are provided for reducing the design size of an integrated circuit while preserving the behavior of the design with respect to verification results. A multiplexer is inserted at the gate being analyzed, and the multiplexer selector is controlled to provide a predetermined output for one frame at the point being analyzed. It is then determined whether the circuit remains equivalent during application of the predetermined output in order to decide whether the gate being analyzed is a candidate for replacement.
1. A method of sequential cofactor-based circuit design for a sequential circuitry netlist, the method comprising:
selecting an arbitrary gate of the sequential circuitry netlist for analysis;
configuring the sequential circuitry netlist to connect the arbitrary gate to a multiplexer;
configuring the sequential circuitry netlist to connect selector control circuitry to a selector input of the arbitrary gate;
detecting a ctime signal applied to said selector input;
in response to the ctime signal, setting the multiplexer output to alter an output of the arbitrary gate; and
determining whether the sequential circuitry behavior remains equivalent during time that the multiplexer output is set to alter the arbitrary gate output.
2. The method of claim 1 , further comprising:
indicating the arbitrary gate as a candidate for replacement upon determining whether the sequential circuitry behavior remains equivalent despite the multiplexer output being set to alter the arbitrary gate output.
3. The method of claim 1 , wherein the configuring of the sequential circuitry netlist to connect the arbitrary gate to a multiplexer further comprises:
connecting the arbitrary gate output to a first input of the multiplexer;
connecting a constant value to a second input of the multiplexer; and
connecting an output of the multiplexer at a point in the sequential circuitry where the arbitrary gate output was previously connected.
4. The method of claim 1 , wherein said ctime signal is applied in response to detecting a human input for controlling the ctime signal.
5. The method of claim 1 , wherein said ctime signal is applied in response to detecting a specific behavior or activity within said circuitry for controlling the ctime signal.
6. The method of claim 5 , wherein said specific behavior or activity is selected from a group consisting of detecting a specific type of instruction at a predetermined interface within said circuitry, detecting a first data buffer filling to a predetermined level, detecting a second data buffer emptying to a predetermined level, detecting a specific request or grant condition at an arbitration unit of the sequential circuitry netlist, and detecting an indication that a predetermined amount of time has elapsed during analysis of the sequential circuitry netlist.
7. The method of claim 1 , wherein the configuring of the sequential circuitry netlist to connect the arbitrary gate to a multiplexer further comprises:
connecting the arbitrary gate output to a first input of the multiplexer;
connecting an inversion of the arbitrary gate output to a second input of the multiplexer; and
connecting an output of the multiplexer at a point in the sequential circuitry where the arbitrary gate output was previously connected.
8. The method of claim 2 , wherein the arbitrary gate is a first random gate, said method further comprising:
selecting a second arbitrary gate of the sequential circuitry for analysis; and
indicating the second arbitrary gate as a candidate for replacement upon determining whether the sequential circuitry behavior remains equivalent despite the multiplexer output being set to alter the second arbitrary gate output.
9. The method of claim 1 , wherein said time that the multiplexer output is set to alter the arbitrary gate output is a single clock period.
10. A software product comprising a program of instructions stored on a non-transitory machine readable device for sequential cofactor-based circuit design of a sequential circuitry netlist wherein the program of instructions upon being executed on a computer causes the computer to perform activities comprising:
selecting an arbitrary gate of the sequential circuitry netlist for analysis;
configuring the sequential circuitry netlist to connect the arbitrary gate to a multiplexer;
configuring the sequential circuitry netlist to connect selector control circuitry to a selector input of the arbitrary gate;
detecting a ctime signal applied to said selector input;
in response to the ctime signal, setting the multiplexer output to alter an output of the arbitrary gate; and
determining whether the sequential circuitry behavior remains equivalent during time that the multiplexer output is set to alter the arbitrary gate output.
11. The product of claim 10 , wherein said computer further causes the computer to perform activities comprising:
indicating the arbitrary gate as a candidate for replacement upon determining whether the sequential circuitry behavior remains equivalent despite the multiplexer output being set to alter the arbitrary gate output.
12. The product of claim 10 , wherein the configuring of the sequential circuitry netlist to connect the arbitrary gate to a multiplexer further comprises:
connecting the arbitrary gate output to a first input of the multiplexer;
connecting a constant value to a second input of the multiplexer; and
connecting an output of the multiplexer at a point in the sequential circuitry where the arbitrary gate output was previously connected.
13. The product of claim 10 , wherein said ctime signal is applied in response to detecting a human input for controlling the ctime signal.
14. The product of claim 10 , wherein said ctime signal is applied in response to detecting a specific behavior or activity within said circuitry for controlling the ctime signal.
15. The product of claim 14 , wherein said specific behavior or activity is selected from a group consisting of detecting a specific type of instruction at a predetermined interface within said circuitry, detecting a first data buffer filling to a predetermined level, detecting a second data buffer emptying to a predetermined level, detecting a specific request or grant condition at an arbitration unit of the sequential circuitry netlist, and detecting an indication that a predetermined amount of time has elapsed during analysis of the sequential circuitry netlist.
16. The product of claim 10 , wherein the configuring of the sequential circuitry netlist to connect the arbitrary gate to a multiplexer further comprises:
connecting the arbitrary gate output to a first input of the multiplexer;
connecting an inversion of the arbitrary gate output to a second input of the multiplexer; and
connecting an output of the multiplexer at a point in the sequential circuitry where the arbitrary gate output was previously connected.
17. The product of claim 10 , wherein the arbitrary gate is a first random gate, said method further comprising:
selecting a second arbitrary gate of the sequential circuitry for analysis.
18. The product of claim 10 , wherein said time that the multiplexer output is set to alter the arbitrary gate output is a single clock period.