Identifying sequential functional paths for IC testing methods and system
View Patent ↗A method and system of identifying sequential functional paths for IC testing methods are disclosed. In one embodiment, a method may include a method of sequential functional path identification for at-speed structural test, the method comprising: using a timing tool to enumerate a plurality of critical paths in a circuit; identifying which of the plurality of critical paths are sequential functional paths that will function during functional operation of the IC by identifying which of the plurality of critical paths a test can be generated for using a test sequence having n functional capture cycles, where n is greater than 2; performing path test generation for the sequential functional paths using launch-off-scan test sequences; and performing path test generation for critical paths not tested by the launch-of-scan test sequences, using launch-off-capture test sequences having two functional captures.
1. A method of sequential functional path identification for at-speed structural test performed on at least one computing device, the method comprising:
using a timing tool to enumerate a plurality of critical paths in a circuit;
identifying, using the at least one computing device, which of the plurality of critical paths are sequential functional paths that will function during functional operation of the IC by identifying which of the plurality of critical paths a test can be generated for using a test sequence having n functional capture cycles, where n is greater than 2;
performing, the at least one computing device, path test generation for the identified sequential functional paths using launch-off-scan test sequences, the launch-off-scan test sequences including applying a single scan shift to all latches in the IC, wherein the single scan shift launches a test transition; and
after the performing of the path test generation using the launch-off scan test sequences, performing, using the at least one computing device, path test generation for critical paths included in the plurality of critical paths not identified and not tested by the launch-off-scan test sequences using launch-off-capture test sequences having two functional captures, the launch-off-capture test sequences including applying a functional capture pulse to the all of the latches in the IC such that the launch-off-capture test captures input data from each functional port of each of the latches.
2. The method of claim 1 , wherein the identifying includes simulating a plurality of random test patterns having n functional capture cycles and identifying as sequential functional paths those critical paths that can be tested using the plurality of random test patterns.
3. The method of claim 1 , wherein the identifying includes attempting to deterministically generate a test pattern having n functional capture cycles for each of the plurality of critical paths, and identifying as sequential functional paths those critical paths that have a deterministic test pattern having n functional captures generated.
4. A system of sequential functional path identification for at-speed structural test, the system comprising:
a component for enumerating a plurality of critical paths in a circuit;
a component for identifying which of the plurality of critical paths are sequential functional paths that will function during functional operation of the IC by identifying which of the plurality of critical paths a test can be generated for using a test sequence having n functional capture cycles, where n is greater than 2;
a component for performing path test generation for the identified sequential functional paths using launch-off-scan test sequences, the launch-off-scan test sequences including applying a single scan shift to all latches in the IC, wherein the single scan shift launches a test transition; and
a component for, after the performing of the path test generation using the launch-off scan test sequences, performing path test generation for critical paths included in the plurality of critical paths not identified and not tested by the launch-off-scan test sequences using launch-off-capture test sequences having two functional captures, the launch-off-capture test sequences including applying a functional capture pulse to the all of the latches in the IC such that the launch-off-capture test captures input data from each functional port of each of the latches.
5. The system of claim 4 , wherein the identifying means simulates a plurality of random test patterns having n functional capture cycles and identifies as sequential functional paths those critical paths that can be tested using the plurality of random test patterns.
6. The system of claim 4 , wherein the identifying means attempts to deterministically generate a test pattern having n functional captures for each of the plurality of critical paths, and identify as sequential functional paths those critical paths that have a deterministic test pattern generated.