Method to identify timing violations outside of manufacturing specification limits
View Patent ↗A method of evaluating an integrated circuit design selects manufacturing parameters of interest which are outside of manufacturing specification limits. Then, the method runs timing tests on the integrated circuit design and successively evaluates the timing test results in an iterative process that considers the timing performance sensitivity to the selected manufacturing parameters of interest. The design is made more robust to each parameter out of manufacturing range.
1. A method of identifying a failing measurement manufacturing parameter in an integrated circuit design using a computer, said method comprising:
selecting, using said computer, a manufacturing measurement parameter of said integrated circuit design;
selecting, using said computer, a timing test on said integrated circuit design;
extrapolating, using said computer, a timing slack of said timing test to obtain an adjusted slack criterion with a higher level of coverage with respect to said manufacturing parameter; and
determining, using said computer, if said adjusted slack is below a required slack in order to identify a failing manufacturing parameter,
wherein said extrapolation comprises one of a linear extrapolation; a quadratic extrapolation, a high-order extrapolation, and a polynomial extrapolation.
2. The method according to claim 1 , wherein said extrapolation comprises a statistical static timing analysis.
3. The method of claim 1 , further comprising applying said extrapolation simultaneously to any subset of measurement manufacturing parameters.
4. The method of claim 1 , wherein said extrapolation is performed to a wafer acceptance criterion (WAC) limit of said measurement manufacturing parameter.
5. A method of identifying a failing measurement manufacturing parameter in an integrated circuit design using a computer, said method comprising:
selecting, using said computer, a manufacturing measurement parameter of said integrated circuit design;
selecting, using said computer, a timing test on said integrated circuit design;
extrapolating, using said computer, a timing slack of said timing test to obtain an adjusted slack criterion with a higher level of coverage with respect to said manufacturing parameter;
determining, using said computer, if said adjusted slack is below a required slack in order to identify a failing manufacturing parameter; and
changing, using said computer, said integrated circuit design with a failing manufacturing parameter to make said integrated circuit design acceptable according to said adjusted slack criterion,
wherein said extrapolation comprises one of a linear extrapolation; a quadratic extrapolation, a high-order extrapolation, and a polynomial extrapolation.