System and method of predicting problematic areas for lithography in a circuit design
View Patent ↗A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.
1. A method, comprising: by a processor
calculating a plane of exposure for one or more tiles of a modeled wafer that best fits modeled surface height data for a predetermined number of values within a slit of a lithography tool;
calculating a distance along an axis of illumination distances of each of the tiles within the slit from the calculated plane; and
identifying at least one of the tiles which are above a predefined specification related to a depth of focus for a lithography process based on the calculated distance along the axis of illumination.
2. The method of claim 1 , wherein the identified tiles are identified as design areas which will be prone to lithography problems at subsequent lithography levels.
3. The method of claim 1 , wherein the identified tiles are fixed by changing a chip design by adjusting at least one of metal patterns and densities.
4. The method of claim 1 , wherein the identified tiles are fixed by changing a chip design by adjusting at least one of metal patterns and densities in other tiles at a level at which a prediction is performed or at one or more underlying metal levels.
5. The method of claim 1 , further comprising repeating the steps of claim 1 .
6. The method of claim 1 , wherein critical images are removed in the identified tiles at a higher level.
7. The method of claim 1 , wherein the identifying is performed by finding the plane which minimizes a sum of the orthogonal distances or a sum of the squares of the orthogonal distances from the plane.
8. The method of claim 1 , wherein the calculating orthogonal distances is performed at a center of each tile, or to a furthest edge or corner of each tile.
9. The method of claim 1 , wherein the steps of claim 1 are implemented on a computing infrastructure.
10. The method of claim 1 , wherein the modeling surface height data is used to accurately predict problematic lithographic areas.
11. The method of claim 1 , wherein the modeling surface height data determines a three dimensional texture of a modeled wafer and the identifying is performed by a modeling tool prior to reticle and wafer fabrication.
12. A design structure embodied in a machine readable memory for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
calculating a plane for one or more tiles of a modeled wafer that best fits modeled surface height data for a predetermined number of values within a slit;
calculating a distance along the axis of illumination distances of each of the tiles within the slit from the calculated plane; and
identifying tiles at least one of the which are above a predefined specification related to a depth of focus for a lithography process based on the calculated distance along the axis of illumination.
13. The design structure of claim 12 , wherein the design structure comprises a netlist.
14. The design structure of claim 12 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
15. The design structure of claim 12 , wherein the design structure resides in a programmable gate array.
16. A memory or storage system storing computer program code that when executed by a processor, causes the processor to perform a method, the method comprising:
calculating a plane of exposure for one or more tiles of a modeled wafer that best fits modeled surface height data for a predetermined number of values within a slit of a lithography tool;
calculating a distance along an axis of illumination distances of each of the tiles within the slit from the calculated plane; and
identifying at least one of the tiles which are above a certain predefined specification related to a depth of focus for a lithography process based on the calculated distance along the axis of illumination.
17. The memory or storage system of claim 16 , wherein the identified tiles are fixed by changing a chip design by adjusting at least one of metal patterns and densities.
18. The memory or storage system of claim 16 , wherein the identified tiles are fixed by changing a chip design by adjusting at least one of metal patterns and densities in other tiles at a level at which a prediction is performed or at one or more underlying metal levels.
19. The memory or storage system of claim 16 , wherein the identifying is performed by finding the plane which minimizes a sum of the orthogonal distances or a sum of the squares of the orthogonal distances from the plane.
20. The memory or storage system of claim 16 , wherein the calculating orthogonal distances is performed at a center of each tile, or to a furthest edge or corner of each tile.