Method for eliminating negative slack in a netlist via transformation and slack categorization
View Patent ↗A method for eliminating negative slack in a netlist representing a chip design uses a contrived timing environment to overlay information onto the design environment during logic and physical synthesis phase. The overlaid timing information determines which netlist transformation provides a maximum leverage for the negative slack elimination and a way for creating a dynamic transformation recipe tuned for each design. The method further provides upper bounds on the negative slack elimination to prevent the netlist transforms from being applied to situations exceeding the capabilities for improving the design.
1. A method of optimizing a design represented by a netlist in a single state of static timing analysis (TA) that determines a minimum achievable slack for a transformation category based on at least another corresponding contrived state of the static timing analysis, the method comprising:
a) using a computer, performing on a first and second TA on the netlist, the first TA measuring a potential impact of a synthesis or netlist transformation on a timing of the design, and the second TA modifying an environment of the first TA to create a more realistic environment in which the netlist transformation is applied to and measured;
b) forming a constraint by transferring an output of the first TA to the second TA;
c) using the constraint, determining which transformations have a greater potential to eliminate a negative slack by performing an optimization on the second TA environment;
d) determining a best transformation to be applied to a current state of the netlist timing by dynamically eliminating a maximum negative slack; and
e) determining that the optimization is achieved without applying particular transformations beyond their respective capabilities, and bounding the negative slack elimination that is applied to a current state of the netlist timing.
2. The method of claim 1 further comprising the step of determining when the transformation applied to the second TA impacts the timing of the first TA environment (TAE), generating changes in the netlist that are reflected back to the first TAE.
3. The method of claim 2 , wherein if a change causes the timing to differ on the first TAE, then updated constraints are forwarded to the second TAE.
4. The method of claim 3 , wherein said first and second TAs are performed concurrently.
5. The method of claim 3 , wherein said first and second TAs are performed sequentially.
6. The method of claim 1 , wherein the netlist transformations are grouped in categories according to a criteria determined by their respective impacts on the netlist timing.
7. The method of claim 6 , wherein based on the constraint generated in the first TA environment, the netlist transformations are altered in a manner where the order of transformation is executed from ones producing a greatest impact to those producing a least impact.
8. The method of claim 1 , wherein slack targets and thresholds are dynamically adjusted to values that are physically implemented by placement and optimization tools.
9. The method of claim 1 , wherein speed of execution is improved by eliminating iterations within the transformations which cannot improve the slack.
10. The method of claim 1 , wherein reports are generated showing a designer portions of the design that cannot be physically implemented, providing an early insight to what prevents the design from reaching zero or a positive slack.
11. An article of manufacture comprising a non-transitory computer usable medium having computer readable program code means embodied therein for causing a chip design represented by a netlist in a single state of static timing analysis (TA) that determines a minimum achievable slack for a transformation category based on at least one other corresponding contrived state of the static timing analysis, the computer readable program code means in said article of manufacture comprising computer readable program code means for causing a computer to effect method steps of:
a) using a computer, performing a first and second TA on the netlist, the first TA measuring a potential impact of a synthesis or netlist transformation on a timing of the design, and the second TA modifying an environment of the first TA to create a more realistic environment in which the netlist transformation is applied to and measured;
b) forming a constraint by transferring an output of the first TA to the second TA;
c) using the constraint, determining which transformations have a greater potential to eliminate a negative slack by performing an optimization on the second TA environment;
d) determining a best transformation to be applied to a current state of the netlist timing by dynamically eliminating a maximum negative slack; and
e) determining that the optimization is achieved without applying particular transformations beyond their respective capabilities, and bounding the negative slack elimination that is applied to a current state of the netlist timing.