Avoiding race conditions at clock domain crossings in an edge based scan design

1. A computer-implemented method of testing clock domains within an integrated circuit structure, said method comprising:

blocking clock inputs to said clock domains using a computer;

while said clock domain inputs are blocked, performing a first timing test only of signals that are transmitted within said clock domains using said computer;

unblocking said clock inputs to said clock domains using said computer; and

while said clock domain inputs are unblocked, performing a second timing test only of signals that are transmitted between said clock domains.

2. The method according to claim 1 , said first timing test comprising simultaneously testing said signals that are transmitted within said clock domains.

3. The method according to claim 1 , said second timing test comprising sequentially testing said signals that are transmitted between said clock domains.

4. The method according to claim 1 , further comprising using a first scan enable signal for said first timing test and using a second scan enable signal for said second timing test, said first scan enable signal being different that said second scan enable signal.

5. The method according to claim 1 , said first timing test and said second timing test comprising alternating current testing using multiple test clock signals delayed from one another.

6. The method according to claim 1 , said first timing test and said second timing test comprising at speed testing using a feedback loop as a toggle to test downstream logic within said clock domains and to block clock signals that are transmitted between said clock domains.

7. A computer-implemented method of testing clock domains within an integrated circuit structure, said method comprising:

blocking clock inputs to said clock domains using test equipment;

while said clock domain inputs are blocked, performing a first timing test only of signals that are transmitted within said clock domains using a computer by only observing latches that receive signals from sources within said clock domains;

unblocking said clock inputs to said clock domains using said computer; and

while said clock domain inputs are unblocked, performing a second timing test only of signals that are transmitted between said clock domains by only observing latches that receive signals from other clock domains.

8. The method according to claim 7 , said first timing test comprising simultaneously testing said signals that are transmitted within said clock domains.

9. The method according to claim 7 , said second timing test comprising sequentially testing said signals that are transmitted between said clock domains.

10. The method according to claim 7 , further comprising using a first scan enable signal for said first timing test and using a second scan enable signal for said second timing test, said first scan enable signal being different that said second scan enable signal.

11. The method according to claim 7 , said first timing test and said second timing test comprising alternating current testing using multiple test clock signals delayed from one another.

12. The method according to claim 7 , said first timing test and said second timing test comprising at speed testing using a feedback loop as a toggle to test downstream logic within said clock domains and to block clock signals that are transmitted between said clock domains.

13. A system for testing clock domains within integrated circuit structures, said system comprising:

an integrated circuit structure;

a plurality of clock domains within said integrated circuit structure, each clock domain comprising a different section of said integrated circuit, and each clock domain operating according to a different clock signal;

controllers positioned within each of said clock domains, said controllers blocking and unblocking clock inputs to said clock domains;

a tester operatively connected to said controllers,

while said clock domain inputs are blocked by said controllers said tester performs a first timing test only of signals that are transmitted within said clock domains by only observing latches that receive signals from sources within said clock domains, and

while said clock domain inputs are unblocked by said controllers, said tester performs a second timing test only of signals that are transmitted between said clock domains by only observing latches that receive signals from other clock domains.

14. The system according to claim 13 , said first timing test comprising simultaneously testing said signals that are transmitted within said clock domains.

15. The system according to claim 13 , said second timing test comprising sequentially testing said signals that are transmitted between said clock domains.

16. The system according to claim 13 , said tester using a first scan enable signal for said first timing test and using a second scan enable signal for said second timing test, said first scan enable signal being different that said second scan enable signal.

17. The system according to claim 13 , said first timing test and said second timing test comprising alternating current testing using multiple test clock signals delayed from one another.

18. The system according to claim 13 , further comprising a feedback loop operatively connected to said controllers, said first timing test and said second timing test comprising at speed testing using said feedback loop as a toggle to test downstream logic within said clock domains and to block clock signals that are transmitted between said clock domains.

19. An integrated circuit structure comprising:

a plurality of clock domains, each clock domain comprising a different section of said integrated circuit, and each clock domain operating according to a different clock signal;

controllers positioned within each of said clock domains, said controllers blocking and unblocking clock inputs to said clock domains;

a processor operatively connected to said clock domains,

while said clock domain inputs are blocked by said controllers said processor performs a first timing test only of signals that are transmitted within said clock domains by only observing latches that receive signals from sources within said clock domains, and

while said clock domain inputs are unblocked by said controllers, said processor performs a second timing test only of signals that are transmitted between said clock domains by only observing latches that receive signals from other clock domains.

20. The structure according to claim 19 , said first timing test comprising simultaneously testing said signals that are transmitted within said clock domains.

21. The structure according to claim 19 , said second timing test comprising sequentially testing said signals that are transmitted between said clock domains.

22. The structure according to claim 19 , said processor using a first scan enable signal for said first timing test and using a second scan enable signal for said second timing test, said first scan enable signal being different that said second scan enable signal.

23. The structure according to claim 19 , said first timing test and said second timing test comprising alternating current testing using multiple test clock signals delayed from one another.

24. The structure according to claim 19 , further comprising a feedback loop operatively connected to said controllers, said first timing test and said second timing test comprising at speed testing using said feedback loop as a toggle to test downstream logic within said clock domains and to block clock signals that are transmitted between said clock domains.