Replicating timing data in static timing analysis operation
View Patent ↗An apparatus, method and program product create multiple copies of a clock signal, or phase, to analyze timing operations within a single timing run of a static timing analysis operation. At least one path comprising logical user defined delay segments and a timing point may be associated with both a common point and no delay. An original clock signal may propagate along the logical path without incurring delay until arriving back at the common point, along with the original signal. All other clocks may be ignored or prevented from propagating long the path. Multiple replicated copies may be accomplished without requiring additional hardware.
1. A method for conducting static timing analysis on an integrated circuit design, the method comprising:
replicating an original clock signal to generate a replicated clock signal by using a computer to assign no delay to a logical path comprising a user defined delay segment coupled to a plurality of user defined timing points, wherein the original clock signal and the replicated clock signal have the same slew;
wherein at least one of the plurality of user defined timing points includes a point traversed by the original clock, configuring the logical path to loop back to the point;
generating the replicated clock signal by propagating the original clock signal through the logical path;
wherein the original clock signal and the replicated clock signal are concurrently modeled within a span of a timing run; and
using the replicated clock signal within a static timing analysis operation associated with an integrated circuit design.
2. The method of claim 1 further comprising replicating the original clock signal multiple times.
3. The method of claim 1 further comprising creating the logical path.
4. The method of claim 3 further comprising associating no delay to a second logical path to generate a second replicated clock signal.
5. The method of claim 1 further comprising naming the replicated clock signal.
6. The method of claim 1 further comprising concurrently propagating the original clock signal through another logical path.
7. The method of claim 1 further comprising disassociating another signal from the logical path.
8. The method of claim 1 further comprising creating the logical path.
9. The method of claim 1 , further comprising outputting both the original and replicated clock signals.
10. An apparatus, comprising:
a processor;
a memory in communication with the processor and storing an integrated circuit design; and
program code resident in the memory, the program code configured to replicate an original clock signal to generate a replicated clock signal by assigning no delay to a logical path comprising a user defined delay segment coupled to a plurality of user defined timing points, wherein the original clock signal and the replicated clock signal have the same slew, wherein at least one of the plurality of user defined timing points includes a point traversed by the original clock, configure the logical path to loop back to the point, generate the replicated clock signal by propagating the original clock signal through the logical path, and to use the replicated clock signal within a static timing analysis operation associated with the integrated circuit design; and wherein the original clock signal and the replicated clock signal are concurrently modeled within a span of a timing run.
11. The apparatus of claim 10 , wherein the program code is further configured to create the logical path.
12. The apparatus of claim 11 , wherein the program code is further configured to disassociate another clock signal from the logical path.
13. A program product embodied in a non-transitory computer readable medium, which when executed by a computer, perform a static timing analysis on an integrated circuit design, comprising:
program code configured to replicate an original clock signal to generate a replicated clock signal by assigning no delay to a logical path comprising a user defined delay segment coupled to a plurality of user defined timing points, wherein the original clock signal and the replicated clock signal have the same slew, wherein at least one of the plurality of user defined timing points includes a point traversed by the original clock, configure the logical path to loop back to the point, generate the replicated clock signal by propagating the original clock signal through the logical path, and to use the replicated clock signal within a static timing analysis operation associated with an integrated circuit design; and
wherein the original clock signal and the replicated clock signal are concurrently moldeled within a span of a timing run.