Computer readable medium, system and associated method for designing integrated circuits with loop insertions
View Patent ↗A computer readable medium, system and associated method is provided for designing an integrated circuit with inserted loops. The method comprises the steps of inserting a loop with tagged wire segments and/or vias in a fully routed and DCR clean integrated circuit; performing a DRC; and fixing DRC violations by removing tagged wire segments and/or vias which contribute to a violation.
1. A computer-implemented method for designing an integrated circuit with inserted loops comprising the steps of:
receiving a routing description at a computing device of an integrated circuit that is fully routed and design rule check (DRC) clean;
inserting a loop in the routing description to form a modified routing description, the loop connecting two elements that were connected together by a first path in the routing description by a second path and being formed with tagged wire segments;
performing a DRC on the modified routing description;
fixing DRC violations by removing tagged wire segments which contribute to a violation.
2. The method of claim 1 , further comprising the step of tagging the wire segments with a special wire type.
3. The method of claim 1 , further comprising a step during which an antenna is removed.
4. The method of claim 1 , further comprising a step of fixing timing violations of the modified routing description.
5. The method of claim 4 , further comprising:
fixing timing violations including ECO (Engineering Change Order) routing ignoring tagged wire segments;
removing shorts to tagged wire segments.
6. The method of claim 4 , wherein the integrated circuit is timing clean.
7. The method of claim 6 , further comprising:
fixing timing violations by removing tagged wire segments which contribute to a violation.
8. A computer readable medium containing computer executable instructions for designing an integrated circuit with inserted loops comprising:
receiving a routing description at a computing device of the integrated circuit that is fully routed and design rule check (DRC) clean;
inserting a loop in the routing description to form a modified routing description, the loop connecting two elements that were connected together by a first path in the routing description by a second path and being formed with tagged wire segments;
performing a DRC on the modified routing description;
fixing DRC violations by removing tagged wire segments which contribute to a violation.