System and method for power reduction through power aware latch weighting

1. A system embodied in a hardware system, comprising:

a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain, each latch being associated with a corresponding bit position;

a don't-care analysis module configured to identify absolute don't-care latches within the DUT;

wherein the don't-care analysis module is further configured to assign a weighted value to the corresponding bit positions of the identified absolute don't-care latches;

wherein the don't-care analysis module is further configured to identify absolute don't-care bits within a general test pattern;

wherein the circuit analysis module is further configured to replace identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, to generate a weighted test pattern;

a test vector module configured to generate a test vector based on the weighted test pattern; and

an input module configured to apply the test vector to the DUT.

2. The system of claim 1 , wherein analyzing a DUT comprises:

determining DUT topography;

identifying logic gates within the DUT; and

determining the logic operation of each identified logic gate.

3. The system of claim 1 , wherein assigning a weighted value comprises:

selecting a value for the bit position associated with each don't-care latch such that the output signal from the logic gate associated with each don't care latch does not change; and

storing the selected value as the weighted value for the latch.

4. The system of claim 1 , further comprising:

a test heuristics module configured to generate test heuristics; and

a test pattern generator module configured to generate the general test pattern based on the test heuristics.

5. The system of claim 1 , further comprising:

wherein the don't-care analysis module is further configured to identify conditional don't-care latches within the DUT;

wherein the don't-care analysis module is further configured to identify conditional don't-care bits within the test pattern; and

wherein the circuit analysis module is further configured to replace identified conditional don't-care bits in the general test pattern according to the weighted value of the associated bit position, to generate a weighted test pattern.

6. The system of claim 1 , wherein:

at least one don't care latch comprises an input to an OR gate; and

the weighted value for the bit position associated with the at least one don't care latch is a logic “1”.

7. The system of claim 1 , wherein:

at least one don't care latch comprises an input to an AND gate; and

the weighted value for the bit position associated with the at least one don't care latch is a logic “0”.

8. A method for power reduction in at-speed test switching through power aware latch weighting, comprising:

analyzing a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain, each latch being associated with a corresponding bit position;

identifying absolute don't-care latches within the DUT;

assigning a weighted value to the corresponding bit positions of the identified absolute don't-care latches;

identifying absolute don't-care bits within a general test pattern;

replacing identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, to generate a weighted test pattern;

generating a test vector based on the weighted test pattern; and

applying the test vector to the DUT.

9. The method of claim 8 , wherein analyzing a DUT comprises:

determining DUT topography;

identifying logic gates within the DUT; and

determining the logic operation of each identified logic gate.

10. The method of claim 8 , wherein assigning a weighted value comprises:

selecting a value for the bit position associated with each don't-care latch such that the output signal from the logic gate associated with each don't care latch does not change; and

storing the selected value as the weighted value for the latch.

11. The method of claim 8 , further comprising:

generating test heuristics; and

generating the general test pattern based on the test heuristics.

12. The method of claim 8 , further comprising:

identifying conditional don't-care latches within the DUT;

identifying conditional don't-care bits within the test pattern; and

replacing identified conditional don't-care bits in the general test pattern according to the weighted value of the associated bit position, to generate a weighted test pattern.

13. The method of claim 8 , wherein:

at least one don't care latch comprises an input to an OR gate; and

the weighted value for the bit position associated with the at least one don't care latch is a logic “1”.

14. The method of claim 8 , wherein:

at least one don't care latch comprises an input to an AND gate; and

the weighted value for the bit position associated with the at least one don't care latch is a logic “0”.

15. A computer program product for power reduction through power aware latch weighting, the computer program product comprising:

a non-transitory computer usable medium having computer useable program code embodied therewith, the computer useable program code comprising:

computer usable program code configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain, each latch being associated with a corresponding bit position;

computer usable program code configured to identify absolute don't-care latches within the DUT;

computer usable program code configured to assign a weighted value to the corresponding bit positions of the identified absolute don't-care latches;

computer usable program code configured to identify absolute don't-care bits within a general test pattern;

computer usable program code configured to replace identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, to generate a weighted test pattern;

computer usable program code configured to generate a test vector based on the weighted test pattern; and

computer usable program code configured to apply the test vector to the DUT.

16. The computer program product of claim 15 , wherein analyzing a DUT comprises:

determining DUT topography;

identifying logic gates within the DUT; and

determining the logic operation of each identified logic gate.

17. The computer program product of claim 15 , wherein assigning a weighted value comprises:

selecting a value for the bit position associated with each don't-care latch such that the output signal from the logic gate associated with each don't care latch does not change; and

storing the selected value as the weighted value for the latch.

18. The computer program product of claim 15 , further comprising:

computer usable program code configured to generate test heuristics; and

computer usable program code configured to generate the general test pattern based on the test heuristics.

19. The computer program product of claim 15 , further comprising:

computer usable program code configured to identify conditional don't-care latches within the DUT;

computer usable program code configured to identify conditional don't-care bits within the test pattern; and

computer usable program code configured to replace identified conditional don't-care bits in the general test pattern according to the weighted value of the associated bit position, to generate a weighted test pattern.

20. The computer program product of claim 15 , wherein:

at least one don't care latch comprises an input to an OR gate; and

the weighted value for the bit position associated with the at least one don't care latch is a logic “1”.

21. The computer program product of claim 15 , wherein:

at least one don't care latch comprises an input to an AND gate; and

the weighted value for the bit position associated with the at least one don't care latch is a logic “0”.