Effective gate length circuit modeling based on concurrent length and mobility analysis
View Patent ↗Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current.
1. A computer implemented method to determine metal oxide semiconductor (MOS) gate functional limitations, the computer implemented method comprising:
obtaining a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width, a slice gate length and a slice stress profile;
determining a drive current for each slice based on a slice gate length and a slice stress profile;
summing the drive currents for each slice to form a gate drive current;
determining a leakage current for each slice based on a slice gate length and a stress profile of the gate;
summing the leakage currents for each slice to form a gate leakage current; and
concurrently determining an effective length for the MOS gate based on the gate drive current and the gate leakage current with determining carrier mobility for the MOS gate based on the gate drive current and the gate leakage current.
2. The computer implemented method of claim 1 , wherein the slice stress profile is obtained by executing instructions on a processor to determine a longitudinal stress in a slice, and applying a transformation to the longitudinal stress to obtain the stress profile.
3. The computer implemented method of claim 1 , wherein the stress profile is based on the addition of an integrated circuit feature selected from a group consisting of a silicon nitride liner layer, silicon germanium source/drain region, and shallow trench isolation.
4. A computer program product comprising computer usable storage device for determining metal oxide semiconductor (MOS) gate functional limitations, comprising:
computer usable program code configured to obtain a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width, a slice gate length and a slice stress profile;
computer usable program code configured to determine a drive current for each slice based on a slice gate length and a slice stress profile;
computer usable program code configured to sum the drive currents for each slice to form a gate drive current;
computer usable program code configured to determine a leakage current for each slice based on a slice gate length and a stress profile of the gate;
computer usable program code configured to sum the leakage currents for each slice to form a gate leakage current; and
computer usable program code configured to concurrently determine an effective length for the MOS gate based on the gate drive current and the gate leakage current with computer usable program code configured to determine carrier mobility for the MOS gate based on the gate drive current and the gate leakage current.
5. The computer program product of claim 4 , further comprising computer usable program code configured to simulate the MOS gate based on the effective length for the MOS gate and the carrier mobility for the MOS gate to determine if the MOS gate functions within tolerances.
6. The computer program product of claim 4 , wherein the slice stress profile is obtained by executing instructions on a processor to determine a longitudinal stress in a slice, and applying a transformation to the longitudinal stress to obtain the stress profile.