Patent Assignment
Reel/Frame 056696/0081
Merger and Change of Name
Recorded: 2021-06-28
Pages: 7
Assignors
MENTOR GRAPHICS CORPORATION
Executed: 2020-12-30
SIEMENS INDUSTRY SOFTWARE INC.
Executed: 2020-12-30
Assignee
SIEMENS INDUSTRY SOFTWARE INC.
5800 GRANITE PARKWAY, SUITE 600, PLANO, TEXAS, 75024
Covered Properties
(93)
Fast and Accurate Method to Simulate Intermediate Range Flare Effects
Method of Performing Timing Analysis on Integrated Circuit Chips with Consideration of Process Variations
System for Quickly Specifying Formal Verification Environments
Effective Gate Length Circuit Modeling Based on Concurrent Length and Mobility Analysis
Accurate Approximation of Resistance in a Wire with Irregular Biasing and Determination of Interconnect Capacitances in Vlsi Layouts in the Presence of Catastrophic Optical Proximity Correction
System, Method, and Computer Program Product for Altering a Hardware Description Based on an Instruction File
Patent:
8,667,434 →
Application:
12/478,658 →
Clock Gating Using Abstraction Refinement
System and Method for Common History Pessimism Relief During Static Timing Analysis
Timing Closure on Multiple Selective Corners in a Single Statistical Timing Run
Method and System to at Least Partially Isolate Nets
Techniques for Performing Conditional Sequential Equivalence Checking of an Integrated Circuit Logic Design
Simultaneous Photolithographic Mask and Target Optimization
Automated Sensitivity Definition and Calibration for Design for Manufacturing Tools
Reduction of Logic and Delay Through Latch Polarity Inversion
System, Method, and Computer Program Product for Reducing a Deactivation Function Utilizing an Optimal Reduction
Patent:
8,621,413 →
Application:
12/723,539 →
Enhanced Analysis of Array-Based Netlists via Reparameterization
Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking Within Designs Including Memory Arrays
System, Method, and Computer Program Product for Conditionally Eliminating a Memory Read Request
Patent:
9,720,859 →
Application:
12/772,051 →
Array Concatenation in an Integrated Circuit Design
Method and Apparatus for Harmonic Balance Using Direct Solution of Hb Jacobian
Patent:
8,473,533 →
Application:
12/818,032 →
Secure Cloud-Based Electronic Design Automation
Layout Decomposition Based on Partial Intensity Distribution
Identification of Fluid Flow Bottlenecks
Equivalence Checking for Retimed Electronic Circuit Designs
System and Method of Predicting Problematic Areas for Lithography in a Circuit Design
Monte-Carlo Based Accurate Corner Extraction
Compact Model Methodology for Pc Landing Pad Lithographic Rounding Impact on Device Performance
Method for Testing Integrated Circuits
Multi-Targeting Boolean Satisfiability-Based Test Pattern Generation
Effective Gate Length Circuit Modeling Based on Concurrent Length and Mobility Analysis
Hotspot Detection Based on Machine Learning
Hybrid Hotspot Detection
Methods and System for Analysis and Management of Parametric Yield
Cell-Aware Fault Model Generation For Delay Faults
Circuit Topology Recognition and Circuit Partitioning
Patent:
8,352,893 →
Application:
13/235,153 →
Simulation and Correction of Mask Shadowing Effect
Parameter Matching Hotspot Detection
Tolerable Flare Difference Determination
Waiving Density Violations
Reliability Evaluation and System Fail Warning Methods Using on Chip Parametric Monitors
Single Event Upset Mitigation for Electronic Design Synthesis
Edge Fragment Correlation Determination for Optical Proximity Correction
Estimation of Power and Thermal Profiles
Pattern Matching Optical Proximity Correction
Compiler for Closed-Loop 1XN Vlsi Design
Compiler for Closed-Loop 1XN Vlsi Design
Encrypted Profiles for Parasitic Extraction
Patent:
8,499,263 →
Application:
13/434,788 →
Methods and System for Analysis and Management of Parametric Yield
Through-Silicon Via Admittance Extraction
Patent:
8,504,962 →
Application:
13/526,442 →
Generating a Convergent Circuit Design from a Functional Description Using Entities Having Access to the Functional Description and to Physical Design Information
Integration of Optical Proximity Correction and Mask Data Preparation
Mask Rule Checking Based on Curvature
Flexible Power Query Interfaces and Infrastructures
Patent:
9,201,994 →
Application:
13/802,083 →
Hardware Simulation Controller, System and Method for Functional Verification
Test-Per-Clock Based on Dynamically-Partitioned Reconfigurable Scan Chains
Rapid Expression Coverage
Controller Area Network (Can) Worst-Case Message Latency with Priority Inversion
Bandwidth Control in a Controller Area Network (Can)
Generating a Convergent Circuit Design from a Functional Description Using Entities Having Access to the Functional Description and to Physical Design Information
Dynamic Control Of Design Clock Generation In Emulation
Generating Guiding Patterns For Directed Self-Assembly
Adaptive Clock Management In Emulation
Determination of Electromigration Susceptibility Based on Hydrostatic Stress Analysis
Selective Parasitic Extraction
Timing Driven Clock Tree Synthesis
Regression Nearest Neighbor Analysis for Statistical Functional Coverage
Social Electronic Design Automation
Regression Signature for Statistical Functional Coverage
System to Combat Design-Time Vulnerability
Patent:
8,930,878 →
Application:
14/168,912 →
Neighbor-Aware Edge Fragment Adjustment for Optical Proximity Correction
Patent:
8,910,098 →
Application:
14/183,209 →
Optical Proximity Correction Based on Edge Fragment Correlation
Patent:
8,881,070 →
Application:
14/183,228 →
Switching Activity Reduction Through Retiming
Circuit Simulation Waveform Generation and Display
Patent:
10,599,881 →
Application:
14/225,274 →
Pattern Optical Similarity Determination
Streaming, at-Speed Debug and Validation Architecture
Metastability Glitch Detection
Reset Verification
Horizontal Development Bias In Negative Tone Development Of Photoresist
Patent:
9,678,435 →
Application:
14/493,073 →
Hierarchical Fill in a Design Layout
Handling Blind Statements In Mixed Language Environments
Circuit Design Layout in Multiple Synchronous Representations
Take Rate Determination
Identification Of High Impedance Nodes In A Circuit Design
Selective Power State Table Composition
Harness Sub-Assembly Rationalization
Three-Dimensional Composite Solid Component Modeling
Logical Equivalency Check with Dynamic Mode Change
Harness Design Change Record and Replay
Constrained Flattening of Design Data
Code Coverage Reconstruction
Signal Integrity Delay Utilizing a Window Bump-Based Aggressor Alignment Scheme
Memory Corruption Protection by Tracing Memory
Multi-Fpga Prototyping of an Asic Circuit
Related Assignments
(20)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 20, 2009
From: SINHA, DEBJIT; FOREMAN, ERIC A.; HABITZ, PETER A.; VENKATESWARAN, NATESAN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 022128/0283 →
Assignment of Assignor's Interest
Feb 16, 2009
From: AUERBACH, GADIEL; GAL, MATAN; NEVO, ZIV
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 022260/0035 →
Assignment of Assignor's Interest
Feb 26, 2009
From: MUKHERJEE, MAHARAJ; CULP, JAMES A.; MANSFIELD, SCOTT M.; LAI, KAFAI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 022316/0331 →
Assignment of Assignor's Interest
Apr 1, 2009
From: AGARWAL, KANAK B.; JOSHI, VIVEK
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 022483/0035 →
Assignment of Assignor's Interest
May 14, 2009
From: DEWEY, III, LEWIS WILLIAM; ELFADEL, IBRAHIM M.; WIDIGER, DAVID J.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 022685/0800 →
Assignment of Assignor's Interest
Jun 4, 2009
From: KIM, VICTOR; DAS, NILOY; SINGH, RAGHVENDRA K.
To: CALYPTO DESIGN SYSTEMS, INC.
Reel/Frame 022795/0971 →
Assignment of Assignor's Interest
Jun 23, 2009
From: ARBEL, ELI; EISNER, CINDY; ROKHLENKO, OLEG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 022860/0034 →
Assignment of Assignor's Interest
Aug 10, 2009
From: FOREMAN, ERIC A.; HABITZ, PETER A.; HATHAWAY, DAVID J.; HEMMETT, JEFFREY G.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 023071/0762 →
Assignment of Assignor's Interest
Sep 1, 2009
From: BUCK, NATHAN C.; DREIBELBIS, BRIAN M.; DUBUQUE, JOHN P.; FOREMAN, ERIC A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 023176/0469 →
Assignment of Assignor's Interest
Sep 11, 2009
From: ECHEGARAY, ALEXANDRA; LAGARES, HEIDI L.; SEARCH, DOUGLAS S.; SZULEWSKI, STEPHEN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 023219/0070 →
Assignment of Assignor's Interest
Oct 16, 2009
From: BAUMGARTNER, JASON R.; CASE, MICHAEL L.; MONY, HARI; SAWADA, JUN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 023382/0217 →
Assignment of Assignor's Interest
Nov 17, 2009
From: AGARWAL, KANAK B.; BANERJEE, SHAYAK; JAMSEK, DAMIR A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 023526/0819 →
Assignment of Assignor's Interest
Jan 5, 2010
From: CULP, JAMES A.; HIBBELER, JASON D.; LIEBMANN, LARS W.; WAGNER, TINA
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 023735/0666 →
Assignment of Assignor's Interest
Jan 12, 2010
From: CHEN, JONATHAN Y.; NEVES, JOSE L.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 023765/0884 →
Assignment of Assignor's Interest
Mar 12, 2010
From: XIE, AIGUO
To: CALYPTO DESIGN SYSTEMS, INC.
Reel/Frame 024078/0188 →
Assignment of Assignor's Interest
Apr 30, 2010
From: TRIPATHI, NIKHIL; RAMACHANDRAN, VENKY; HALDAR, MALAY; ROY, SUMIT
To: CALYPTO DESIGN SYSTEMS, INC.
Reel/Frame 024322/0322 →
Assignment of Assignor's Interest
May 10, 2010
From: BAUMGARTNER, JASON R.; CASE, MICHAEL L.; KANZELMAN, ROBERT L.; MONY, HARI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 024362/0037 →
Assignment of Assignor's Interest
May 10, 2010
From: BAUMGARTNER, JASON R.; CASE, MICHAEL L.; KANZELMAN, ROBERT L.; MONY, HARI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 024362/0017 →
Assignment of Assignor's Interest
Feb 1, 2013
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 029733/0156 →
Assignment of Assignor's Interest
Dec 13, 2018
From: CALYPTO DESIGN SYSTEMS, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 047766/0077 →