Logical equivalency check with dynamic mode change

1. A method comprising:

identifying, by a computing system, matched register pairs, each having one register in a first circuit design and one register in a second circuit design;

determining, by the computing system in a combinational equivalence check mode, a portion of combinational logic, corresponding to a first matched register pair, in the first circuit design is not equivalent to a portion of combinational logic, corresponding to the first matched register pair, in the second circuit design;

switching the computing system from the combinational equivalence check mode to a sequential equivalence check mode;

sequentially expanding, by the computing system in the sequential equivalence check mode, the portions of the combinational logic in the first circuit design and the second circuit design by coupling the portions of the combinational logic corresponding to the first matched register pair to combinational logic corresponding to a second matched register pair; and

determining, by the computing system, whether the expanded portion of the combinational logic in the first circuit design is equivalent to the expanded portion of the combinational logic in the second circuit design.

2. The method of claim 1 , further comprising outputting, by the computing system, a signal configured to indicate an equivalence between the expanded portion of the combinational logic in the first circuit design and the expanded portion of the combinational logic in the second circuit design.

3. The method of claim 1 , wherein sequentially expanding the portions of the combinational logic in the first circuit design and the second circuit design further comprises coupling outputs from the portions of the combinational logic in the first circuit design and the second circuit design to inputs to additional portions of the combinational logic in the first circuit design and the second circuit design.

4. The method of claim 1 , wherein output of the first matched register pair is input into the combinational logic corresponding to the second matched register pair.

5. The method of claim 1 , further comprising:

when the expanded portions of the combinational logic in the first circuit design and the second circuit design are not equivalent, sequentially re-expanding, by the computing system, the expanded portions of the combinational logic in the first circuit design and the second circuit design; and

determining, by the computing system, whether the re-expanded portion of the combinational logic in the first circuit design is equivalent to the re-expanded portion of the combinational logic in the second circuit design.

6. A system comprising:

a memory system configured to store computer-executable instructions; and

a computing system, in response to execution of the computer-executable instructions, is configured to:

identify matched register pairs, each having one register in the first circuit design and one register in the second circuit design;

determine, in a combinational equivalence check mode, a portion of combinational logic, corresponding to a first matched register pair, in the first circuit design is not equivalent to a portion of combinational logic, corresponding to the first matched register pair, in the second circuit design;

switch the computing system from the combinational equivalence check mode to a sequential equivalence check mode;

sequentially expand, in the sequential equivalence check mode, the portions of the combinational logic in the first circuit design and the second circuit design by coupling the portions of the combinational logic corresponding to the first matched register pair to combinational logic corresponding to a second matched register pair; and

determine whether the expanded portion of the combinational logic in the first circuit design is equivalent to the expanded portion of the combinational logic in the second circuit design.

7. The system of claim 6 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to output a signal configured to indicate an equivalence between the expanded portion of the combinational logic in the first circuit design and the expanded portion of the combinational logic in the second circuit design.

8. The system of claim 6 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to sequentially expand the portions of the combinational logic in the first circuit design and the second circuit design by coupling outputs from the portions of the combinational logic in the first circuit design and the second circuit design to inputs to additional portions of the combinational logic in the first circuit design and the second circuit design.

9. The system of claim 6 , wherein output of the first matched register pair is input into the combinational logic corresponding to the second matched register pair.

10. The system of claim 6 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to:

sequentially re-expand the expanded portions of the combinational logic in the first circuit design and the second circuit design when the expanded portions of the combinational logic in the first circuit design and the second circuit design are not equivalent; and

determine whether the re-expanded portion of the combinational logic in the first circuit design is equivalent to the re-expanded portion of the combinational logic in the second circuit design.

11. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

identifying matched register pairs, each having one register in the first circuit design and one register in the second circuit design;

determining, in a combinational equivalence check mode, a portion of combinational logic, corresponding to a first matched register pair, in the first circuit design is not equivalent to a portion of combinational logic, corresponding to the first matched register pair, in the second circuit design;

switching from the combinational equivalence check mode to a sequential equivalence check mode;

sequentially expanding, in the sequential equivalence check mode, the portions of the combinational logic in the first circuit design and the second circuit design by coupling the portions of the combinational logic corresponding to the first matched register pair to combinational logic corresponding to a second matched register pair; and

determining whether the expanded portion of the combinational logic in the first circuit design is equivalent to the expanded portion of the combinational logic in the second circuit design.

12. The apparatus of claim 11 , wherein the instructions are configured to cause the one or more processing devices to perform operations further comprising

recording equivalence determinations for each portion of the combinational logic and expanded portion of the combinational logic; and

generating an equivalence output to indicate whether the combinational logic in the first circuit design is equivalent to the combinational logic in a second circuit design.

13. The apparatus of claim 11 , wherein sequentially expanding the portions of the combinational logic in the first circuit design and the second circuit design further comprises coupling outputs from the portions of the combinational logic in the first circuit design and the second circuit design to inputs to additional portions of the combinational logic in the first circuit design and the second circuit design.

14. The apparatus of claim 11 , wherein output of the first matched register pair is input into the combinational logic corresponding to the second matched register pair.

15. The apparatus of claim 11 , wherein the instructions are configured to cause the one or more processing devices to perform operations further comprising:

when the expanded portions of the combinational logic in the first circuit design and the second circuit design are not equivalent, sequentially re-expanding the expanded portions of the combinational logic in the first circuit design and the second circuit design; and

determining whether the re-expanded portion of the combinational logic in the first circuit design is equivalent to the re-expanded portion of the combinational logic in the second circuit design.