Encrypted profiles for parasitic extraction

1. A method of generating encrypted profiles for layout features, comprising:

with a computer, receiving layout design and process profile data for a layout feature;

partitioning the layout feature into a plurality of subdomains, the plurality of subdomains being associated with boundary nodes and internal nodes, the boundary nodes comprising points on boundary of the layout feature and points on conductors inside the boundary of the layout feature, the internal nodes being points inside the boundary of the layout feature;

generating, based on the layout design and process profile data, a first model describing a first electric parameter relationship involving the boundary nodes and the internal nodes;

generating, based on the first model, a second model describing a second electric parameter relationship involving the boundary nodes; and

outputting the second model and location information of the boundary nodes as an encrypted profile for the layout feature.

2. The method recited in claim 1 , wherein the layout feature comprises one or more geometric elements corresponding to a portion of or a whole of a device.

3. The method recited in claim 2 , wherein the device is a transistor.

4. The method recited in claim 3 , wherein the portion of the transistor is gate portion of the transistor.

5. The method recited in claim 1 , wherein the layout design and process profile data comprising electric susceptibility or permittivity information for dielectric materials in the layout feature and conductor information.

6. The method recited in claim 1 , wherein the first model and the second model are finite difference method models.

7. The method recited in claim 1 , wherein the first electric parameter relationship and the second electric parameter relationship are relationships of electric field flux vs. electric potential.

8. The method recited in claim 1 , further comprising:

extracting one or more parasitic parameters associated with the layout feature based on the second model.

9. The method recited in claim 8 , wherein the one or more parasitic parameters comprise parasitic capacitance.

10. A non-volatile processor-readable medium storing processor-executable instructions for causing one or more processors to perform a method of generating encrypted profiles for layout features, the method comprising:

receiving layout design and process profile data for a layout feature;

partitioning the layout feature into a plurality of subdomains, the plurality of subdomains being associated with boundary nodes and internal nodes, the boundary nodes comprising points on boundary of the layout feature and points on conductors inside the boundary of the layout feature, the internal nodes being points inside the boundary of the layout feature;

generating, based on the layout design and process profile data, a first model describing a first electric parameter relationship involving the boundary nodes and the internal nodes;

generating, based on the first model, a second model describing a second electric parameter relationship involving the boundary nodes; and

outputting the second model and location information of the boundary nodes as an encrypted profile for the layout feature.

11. The processor-readable medium recited in claim 10 , wherein the layout feature comprises one or more geometric elements corresponding to a portion of or a whole of a device.

12. The processor-readable medium recited in claim 10 , wherein the first model and the second model are finite difference method models.

13. The processor-readable medium recited in claim 10 , wherein the first electric parameter relationship and the second electric parameter relationship are relationships of electric field flux vs. electric potential.

14. The processor-readable medium recited in claim 10 , wherein the method further comprises:

extracting one or more parasitic parameters associated with the layout feature based on the second model.

15. A system for generating encrypted profiles for layout features, comprising:

a partition unit configurable to partition a layout feature into a plurality of subdomains, the plurality of subdomains being associated with boundary nodes and internal nodes, the boundary nodes comprising points on boundary of the layout feature and points on conductors inside the boundary of the layout feature, the internal nodes being points inside the boundary of the layout feature;

an initial model generation unit configurable to generate, based on layout design and process profile data for the layout feature, a first model describing a first electric parameter relationship involving the boundary nodes and the internal nodes;

a final model generation unit configurable to generate, based on the first model, a second model describing a second electric parameter relationship involving the boundary nodes.

16. The system recited in claim 15 , wherein the layout feature comprises one or more geometric elements corresponding to a portion of or a whole of a device.

17. The system recited in claim 15 , wherein the first model and the second model are finite difference method models.

18. The system recited in claim 15 , wherein the first electric parameter relationship and the second electric parameter relationship are relationships of electric field flux vs. electric potential.

19. The system recited in claim 15 , wherein the method further comprises:

extracting one or more parasitic parameters associated with the layout feature based on the second model.