Cell-aware fault model generation for delay faults
View Patent ↗Cell-aware fault models for delay faults are created for library cells. Analog one-clock-cycle fault simulations are first performed on a transistor-level netlist of a cell to identify type one detectable defects and type two detectable defects in defects of interest. The type one detectable defects are detectable by one-clock-cycle testing and their fault models may be created based on results of the analog one-clock-cycle fault simulations. The type two detectable defects are defects for which two-cycle detection conditions may be calculated from corresponding results of the analog one-cycle fault simulations. Analog two-clock-cycle fault simulations are then performed for the rest defects in the defects of interest to determine type three detectable defects and their detection conditions. The created cell-aware fault models may be used to generate cell-aware test patterns.
1. A method of cell-aware fault model generation, executed by at least one processor of a computer, comprising:
receiving a transistor-level netlist and defects of interest for a cell;
performing, at least one processor of a computer, analog one-cycle fault simulations based on the transistor-level netlist to identify type one detectable defects and type two detectable defects in the defects of interest;
determining calculated two-cycle detection conditions for the type two detectable defects based on results of the analog one-cycle fault simulations for the type two detectable defects;
performing analog two-cycle fault simulations based on the transistor-level netlist and the defects of interest, the type one detectable defects and the type two detectable defects to determine type three detectable defects and simulated two-cycle detection conditions for the type three detectable defects;
generating two-cycle cell-aware fault models for two-cycle testing of the type two detectable defects and the type three detectable defects based on the calculated two-cycle detection conditions and the simulated two-cycle detection conditions; and
storing the two-cycle cell-aware fault models for two-cycle testing of the type two detectable defects and the type three detectable defects.
2. The method recited in claim 1 , wherein the transistor-level netlist is extracted from layout data of the cell.
3. The method recited in claim 1 , further comprising:
generating one-cycle cell-aware fault models for one-cycle testing of the type one detectable defects based on results of the analog one-cycle fault simulations for the type one detectable defects; and
storing the one-cycle cell-aware fault models for one-cycle testing.
4. The method recited in claim 1 , further comprising:
generating test patterns based on the two-cycle cell-aware fault models.
5. The method recited in claim 1 , wherein the defects of interest is determined based on layout data of the cell and the transistor-level netlist.
6. The method recited in claim 1 , wherein the type one detectable defects are defects that can be detected by one-cycle testing and the type two detectable defects are defects for which two-cycle detection conditions may be calculated without performing analog two-cycle fault simulations.
7. The method recited in claim 1 , wherein the type one detectable defects are defects that can cause one or more outputs of the cell to output a voltage that deviates from a golden voltage by a percentage of the golden voltage less than a first predetermined number, and the type two detectable defects are defects that can cause one or more outputs of the cell to output a voltage that deviates from the golden voltage by a percentage of the golden voltage between the first predetermined value and a second predetermined value.
8. The method recited in claim 1 , wherein the performing analog one-cycle fault simulation comprises:
selecting a defect from the defects of interest;
inserting the defect into the transistor-level netlist to generate a modified transistor-level netlist; and
performing analog one-cycle fault simulations on the modified transistor-level netlist to determine whether the defect is a type one detectable defect, a type two detectable defect or else.
9. The method recited in claim 8 , wherein the performing analog one-cycle fault simulation further comprises:
generating a detection matrix based on results of the analog one-cycle fault simulations for the type one detectable defects.
10. The method recited in claim 1 , wherein the determining calculated two-cycle detection conditions comprises:
determining final time frame stimuli based on results of the analog one-cycle fault simulations for the type two detectable defects;
determining initial time frame stimuli based on the final time frame stimuli; and
determining calculated two-cycle detection conditions based on the final time frame stimuli, the initial time frame stimuli and the results of the analog one-cycle fault simulations for the type two detectable defects.
11. The method recited in claim 1 , wherein the performing analog two-cycle fault simulations comprises:
determining type three defect candidates based on the defects of interest, the type one detectable defects and the type two detectable defects;
selecting a defect from the type three defect candidates;
injecting the defect into the transistor-level netlist to generate a modified transistor-level netlist; and
performing analog two-cycle fault simulations on the modified transistor-level netlist to determine whether the defect is a type three detectable defect, and to derive simulated two-cycle detection conditions if the defect is a type three detectable defect.
12. The method recited in claim 1 , wherein the performing analog two-cycle fault simulations comprises employing a robust two-cycle test generation technique.
13. The method recited in claim 1 , wherein the generating two-cycle cell-aware fault models comprises:
generating prime cubes by determining necessary input combinations based on the calculated two-cycle detection conditions and the simulated two-cycle detection conditions, the necessary input combinations being input combinations required to detect the defects without don't cares; and
combining the prime cubes with corresponding output combinations.
14. The method recited in claim 13 , wherein generating two-cycle cell-aware fault models further comprises:
compressing identical prime cubes to generate a set of compressed prime cubes and a set of defect lists, each defect list denoting defects that can be detected by a compressed prime cube.
15. A non-transitory processor-readable medium storing processor-executable instructions for causing one or more processors to perform a method of cell-aware fault model generation, the method comprising:
receiving a transistor-level netlist and defects of interest for a cell;
performing analog one-cycle fault simulations based on the transistor-level netlist to identify type one detectable defects and type two detectable defects in the defects of interest;
determining calculated two-cycle detection conditions for the type two detectable defects based on results of the analog one-cycle fault simulations for the type two detectable defects;
performing analog two-cycle fault simulations based on the transistor-level netlist and the defects of interest, the type one detectable defects and the type two detectable defects to determine type three detectable defects and simulated two-cycle detection conditions for the type three detectable defects;
generating two-cycle cell-aware fault models for two-cycle testing of the type two detectable defects and the type three detectable defects based on the calculated two-cycle detection conditions and the simulated two-cycle detection conditions; and
storing the two-cycle cell-aware fault models for two-cycle testing of the type two detectable defects and the type three detectable defects.
16. The non-transitory processor-readable medium recited in claim 15 , wherein the transistor-level netlist is extracted from layout data of the cell.
17. The non-transitory processor-readable medium recited in claim 15 , wherein the method further comprises:
generating one-cycle cell-aware fault models for one-cycle testing of the type one detectable defects based on results of the analog one-cycle fault simulations for the type one detectable defects; and
storing the one-cycle cell-aware fault models for one-cycle testing.
18. The non-transitory processor-readable medium recited in claim 15 , wherein the defects of interest is determined based on layout data of the cell and the transistor-level netlist.
19. The non-transitory processor-readable medium recited in claim 15 , wherein the type one detectable defects are defects that can be detected by one-cycle testing and the type two detectable defects are defects for which two-cycle detection conditions may be calculated without performing analog two-cycle fault simulations.
20. The non-transitory processor-readable medium recited in claim 15 , wherein the determining calculated two-cycle detection conditions comprises:
determining final time frame stimuli based on results of the analog one-cycle fault simulations for the type two detectable defects;
determining initial time frame stimuli based on the final time frame stimuli; and
determining calculated two-cycle detection conditions based on the final time frame stimuli, the initial time frame stimuli and the results of the analog one-cycle fault simulations for the type two detectable defects.
21. The non-transitory processor-readable medium recited in claim 15 , wherein the performing analog two-cycle fault simulations comprises:
determining type three defect candidates based on the defects of interest, the type one detectable defects and the type two detectable defects;
selecting a defect from the type three defect candidates;
injecting the defect into the transistor-level netlist to generate a modified transistor-level netlist; and
performing analog two-cycle fault simulations on the modified transistor-level netlist to determine whether the defect is a type three detectable defect, and to derive simulated two-cycle detection conditions if the defect is a type three detectable defect.
22. A system of cell-aware fault model generation comprising:
an analog one-cycle simulation unit configured to perform analog one-cycle fault simulations based on a transistor-level netlist for a cell to identify type one detectable defects and type two detectable defects in defects of interest for the cell;
a two-cycle calculation unit configured to determine calculated two-cycle detection conditions for the type two detectable defects based on results of the analog one-cycle fault simulations for the type two detectable defects;
an analog two-cycle simulation unit configured to perform analog two-cycle fault simulations based on the transistor-level netlist and the defects of interest, the type one detectable defects and the type two detectable defects to determine type three detectable defects and simulated two-cycle detection conditions for the type three detectable defects; and
a fault model synthesis unit configured to generate two-cycle cell-aware fault models for two-cycle testing of the type two detectable defects and the type three detectable defects based on the calculated two-cycle detection conditions and the simulated two-cycle detection conditions.
23. The system recited in claim 22 , wherein the transistor-level netlist is extracted from layout data of the cell.
24. The system recited in claim 22 , wherein the defects of interest is determined based on layout data of the cell and the transistor-level netlist.
25. The system recited in claim 22 , wherein the type one detectable defects are defects that can be detected by one-cycle testing and the type two detectable defects are defects for which two-cycle detection conditions may be calculated without performing analog two-cycle fault simulations.
26. The system recited in claim 22 , wherein the fault model synthesis unit is also configured to generate one-cycle cell-aware fault models for one-cycle testing of the type one detectable defects based on results of the analog one-cycle fault simulations for the type one detectable defects.