Equivalence checking for retimed electronic circuit designs
View Patent ↗Techniques and technology for formally verifying a first electronic design with a second electronic design that has been synthesized from the first electronic design, wherein the synthesis process included structural transformation operations, is provide herein. In various implementations, a first design and a second design are received. The second design having been synthesized from the first design, where no structural transformation operations were performed during synthesis of the second design. Additionally, a third design and a structural transformation guidance file are received. The third design having also been synthesized from the first design, but, where structural transformation operations were performed during synthesis of the third design. The structural transformation guidance file specifies what transformations where made during synthesis. Subsequently, a first formal verification process is implemented to verify the equivalence of the first design to the second design using conventional formal verification proofs. A modified second design is then generated, by applying changes to the second design to correspond to the structural transformations detailed in the structural transformation guidance file. After which, a second formal verification process is implemented to verify the equivalence of the third design and the modified second design.
1. A computer-implemented method for performing formal verification, the method comprising:
accessing a first electronic design;
accessing a second electronic design, the second electronic design having been synthesized from the first electronic design using a synthesis process that did not include any retiming operations;
accessing a third electronic design, the third electronic design having been synthesized from the first electronic design using a synthesis process that included one or more retiming operations;
receiving a retiming guidance file corresponding to the one or more retiming operations;
implementing a first formal verification process on the first electronic design and the second electronic design, wherein a first result is obtained;
modifying the second electronic design based in part upon the retiming guidance file;
implementing a second formal verification process on the modified second electronic design and the third electronic design, wherein a second result is obtained;
comparing the first result to the second result to generate a comparison result; and
saving the comparison result to one or more memory storage locations.
2. The computer-implemented method recited in claim 1 , further comprising determining if the first electronic design and the third electronic design are logically equivalent based in part on the comparison result.
3. The computer-implemented method recited in claim 2 , wherein determining if the first electronic design and the third electronic design are logically equivalent identifies one or more areas of the first electronic design and the third electronic design that are not logically equivalent, the method further comprising:
generating a report detailing the one or more identified areas; and
making the report available to a user of the method.
4. The computer-implemented method recited in claim 1 , wherein:
the first electronic design is described at a register transfer level;
the second electronic design is described at a gate-level; and
the third electronic design is described at a gate-level.
5. The computer-implemented method recited in claim 1 , wherein implementing the first formal verification process on the first electronic design and the second electronic design, comprises:
generating a first set of formal verification statements, the first set of formal verification statements describing a logical operation of the first electronic design;
generating a second set of formal verification statements, the second set of formal verification statements describing a logical operation of the second electronic design; and
comparing the first set of formal verification statements and the second set of formal verification statements based in part upon logical proofs.
6. The computer-implemented method recited in claim 5 , wherein implementing the second formal verification process on the modified second electronic design and the third electronic design comprises:
generating a third set of formal verification statements, the third set of formal verification statements describing a logical operation of the modified second electronic design;
generating a fourth set of formal verification statements, the fourth set of formal verification statements describing a logical operation of the third electronic design; and
comparing the third set of formal verification statements and the fourth set of formal verification statements based in part upon logical proofs.
7. One or more non-transitory computer-readable media, having computer executable instructions stored thereon for performing a formal verification method comprising:
accessing a first electronic design;
accessing a second electronic design, the second electronic design having been synthesized from the first electronic design using a synthesis process that did not include any retiming operations;
accessing a third electronic design, the third electronic design having been synthesized from the first electronic design using a synthesis process that included one or more retiming operations;
receiving a retiming guidance file corresponding to the one or more retiming operations;
implementing a first formal verification process on the first electronic design and the second electronic design, wherein a first result is obtained;
modifying the second electronic design based in part upon the retiming guidance file;
implementing a second formal verification process on the modified second electronic design and the third electronic design, wherein a second result is obtained;
comparing the first result to the second result to generate comparison results; and
saving the comparison results to one or more memory storage locations.
8. The one or more non-transitory computer-readable media recited in claim 7 , wherein the formal verification method further comprises determining if the first electronic design and the third electronic design are logically equivalent based in part on the comparison results.
9. The one or more non-transitory computer-readable media recited in claim 8 , wherein determining if the first electronic design and the third electronic design are logically equivalent identifies one or more areas of the electronic design that are not logically equivalent, and wherein the formal verification method further comprises:
generating a report detailing the one or more identified areas; and
making the report available to a user of the non-transitory computer-readable media.
10. The one or more non-transitory computer-readable media recited in claim 7 , wherein:
the first electronic design is described at a register transfer level;
the second electronic design is described at a gate-level; and
the third electronic design is described at a gate-level.
11. The one or more non-transitory computer-readable media recited in claim 7 , wherein implementing the first formal verification process on the first electronic design and the second electronic design comprises:
generating a first set of formal verification statements, the first set of formal verification statements describing a logical operation of the first electronic design;
generating a second set of formal verification statements, the second set of formal verification statements describing a logical operation of the second electronic design; and
comparing the first set of formal verification statements and the second set of formal verification statements based in part upon logical proofs.
12. The one or more non-transitory computer-readable media recited in claim 11 , wherein implementing the second formal verification process on the modified second electronic design and the third electronic design comprises:
generating a third set of formal verification statements, the third set of formal verification statements describing a logical operation of the modified second electronic design;
generating a fourth set of formal verification statements, the fourth set of formal verification statements describing a logical operation of the third electronic design; and
comparing the third set of formal verification statements and the fourth set of formal verification statements based in part upon logical proofs.