Circuit topology recognition and circuit partitioning
View Patent ↗Aspects of the invention relate to circuit topology recognition and circuit partitioning. In various embodiments of the invention, diode-connected transistors can be identified in a circuit netlist based on the unique structure. From the diode-connected transistors, current mirrors can be found. The current mirrors may be employed for locating differential pairs used in the input stage of operational amplifiers and for locating supply voltage and ground nodes in the netlist. The subcircuits that are strongly connected due to feedback loops of operational amplifiers in the circuit can then be identified and grouped together for circuit analysis and simulation.
1. A method of circuit topology recognition, executed by at least one processor of a computer, comprising:
receiving transistor-level netlist data for a circuit;
identifying one or more current mirrors in the circuit by analyzing the transistor-level netlist data by using the at least one processor of the computer;
partitioning the circuit into a plurality of subcircuits;
identifying a differential pair in the circuit based on the one or more current mirrors;
determining one or more outputs of a differential pair subcircuit, the differential pair subcircuit being the subcircuit in which the differential pair is located;
identifying one or more strongly connected subcircuits in the plurality of subcircuits that form a feedback loop with the differential pair subcircuit based on the one or more outputs; and
grouping the one or more strongly connected subcircuit and the differential pair subcircuit into one subcircuit for circuit analysis, circuit simulation or both.
2. The method recited in claim 1 , wherein the circuit simulation is a Fast-SPICE simulation.
3. The method recited in claim 1 , wherein the circuit is a subcircuit of a large circuit design.
4. The method recited in claim 1 , wherein the identifying one or more current mirrors comprises:
identifying diode-connected transistors in the transistor-level netlist; and
identifying one or more current mirrors based on the diode-connected transistors.
5. The method recited in claim 1 , wherein the partitioning the circuit is based on the one or more current mirrors.
6. The method recited in claim 1 , wherein the partitioning the circuit comprises:
identifying voltage-reference nodes based on source/emitter terminals of transistors in the one or more current mirrors.
7. The method recited in claim 1 , wherein the plurality of subcircuits are a plurality of DC-connected components, the differential pair subcircuit is a differential pair DC-connected component, and the one or more feedback loop subcircuits are the one or more feedback loop DC-connected components.
8. The method recited in claim 1 , wherein the identifying a differential pair comprises:
searching for a differential pair from drain/collector terminals of transistors in one of the one or more current mirrors.
9. The method recited in claim 1 , wherein the identifying a differential pair comprises:
searching for a differential pair from drain/collector terminals of mirror transistors in one of the one or more current mirrors.
10. The method recited in claim 1 , wherein the one or more outputs of the differential pair subcircuits is determined by tracing along one or two low impedance paths starting from the differential pair.
11. The method recited in claim 10 , wherein the one or two low impedance paths are determined based on low impedance and high impedance rules.
12. The method recited in claim 11 , wherein the low impedance and high impedance rules comprises:
low impedance nodes comprising a source/emitter terminal of a current buffer, a drain/collector terminal of a diode-connected transistor, and a compound resistor with resistance less than a predetermined value; and
high impedance nodes comprising drain/collector terminals of one or more transistors; a compound resistor with resistance greater than or equal to a predetermined value, and an RC network terminated by a ground node or a supply voltage node.
13. A non-transitory processor-readable medium storing processor-executable instructions for causing one or more processors to perform a method of circuit topology recognition, the method comprising:
receiving transistor-level netlist data for a circuit;
identifying one or more current mirrors in the circuit by analyzing the transistor-level netlist data;
partitioning the circuit into a plurality of subcircuits;
identifying a differential pair in the circuit based on the one or more current mirrors;
determining one or more outputs of a differential pair subcircuit, the differential pair subcircuit being the subcircuit in which the differential pair is located;
identifying one or more strongly connected subcircuits in the plurality of subcircuits that form a feedback loop with the differential pair subcircuit based on the one or more outputs; and
grouping the one or more strongly connected subcircuits and the differential pair subcircuit into one subcircuit for circuit analysis, circuit simulation or both.
14. The non-transitory processor-readable medium recited in claim 13 , wherein the identifying one or more current mirrors comprises:
identifying diode-connected transistors in the transistor-level netlist; and
identifying one or more current mirrors based on the diode-connected transistors.
15. The non-transitory processor-readable medium recited in claim 13 , wherein the partitioning the circuit comprises:
identifying a supply voltage node, a ground node or both based on source/emitter terminals of transistors in the one or more current mirrors.
16. The non-transitory processor-readable medium recited in claim 13 , wherein the identifying a differential pair comprises:
searching for a differential pair from drain/collector terminals of transistors in one of the one or more current mirrors.
17. The non-transitory processor-readable medium recited in claim 13 , wherein the one or more outputs of the differential pair subcircuits is determined by tracing along one or two low impedance paths starting from the differential pair.
18. The non-transitory processor-readable medium recited in claim 17 , wherein the one or two low impedance paths are determined based on low impedance and high impedance rules.
19. The non-transitory processor-readable medium recited in claim 18 , wherein the low impedance and high impedance rules comprises:
low impedance nodes comprising a source/emitter terminal of a current buffer, a drain/collector terminal of a diode-connected transistor, and a compound resistor with resistance less than a predetermined value; and
high impedance nodes comprising drain/collector terminals of one or more transistors; a compound resistor with resistance greater than or equal to a predetermined value, and an RC network terminated by a ground node or a supply voltage node.
20. A system comprising:
one or more processors, the one or more processors programmed to perform a method of circuit topology recognition, the method comprising:
receiving transistor-level netlist data for a circuit;
identifying one or more current mirrors in the circuit by analyzing the transistor-level netlist data;
partitioning the circuit into a plurality of subcircuits;
identifying a differential pair in the circuit based on the one or more current mirrors;
determining one or more outputs of a differential pair subcircuit, the differential pair subcircuit being the subcircuit in which the differential pair is located;
identifying one or more strongly connected subcircuits in the plurality of subcircuits that form a feedback loop with the differential pair subcircuit based on the one or more outputs; and
grouping the one or more strongly connected subcircuits and the differential pair subcircuit into one subcircuit for circuit analysis, circuit simulation or both.
21. The system recited in claim 20 , wherein the identifying one or more current mirrors comprises:
identifying diode-connected transistors in the transistor-level netlist; and
identifying one or more current mirrors based on the diode-connected transistors.
22. The system recited in claim 20 , wherein the partitioning the circuit comprises:
identifying a supply voltage node, a ground node or both based on source/emitter terminals of transistors in the one or more current mirrors.
23. The system recited in claim 20 , wherein the identifying a differential pair comprises:
searching for a differential pair from drain/collector terminals of transistors in one of the one or more current mirrors.
24. The system recited in claim 20 , wherein the one or more outputs of the differential pair subcircuits is determined by tracing along one or two low impedance paths starting from the differential pair.
25. The system recited in claim 24 , wherein the one or two low impedance paths are determined based on low impedance and high impedance rules.
26. The system recited in claim 25 , wherein the low impedance and high impedance rules comprises:
low impedance nodes comprising a source/emitter terminal of a current buffer, a drain/collector terminal of a diode-connected transistor, and a compound resistor with resistance less than a predetermined value; and
high impedance nodes comprising drain/collector terminals of one or more transistors; a compound resistor with resistance greater than or equal to a predetermined value, and an RC network terminated by a ground node or a supply voltage node.