Method and system for efficient validation of clock skews during hierarchical static timing analysis
View Patent ↗A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.
1. A method for conducting a static timing analysis on a top-level design having at least one hierarchical module, the method comprising:
using a computer system for:
asserting arrival times on a plurality of clock inputs of at least one of said hierarchical modules;
for at least one pair of the plurality of clock inputs, determining a clock input slack based on propagating the asserted clock input arrival times and determining a largest allowable clock skew as a function of said asserted arrival times at said clock inputs, and
performing a top-level analysis of the at least one hierarchical design, during which said largest allowable clock skew of said at least one pair of clock signals is used to compute a clock skew slack.
2. The method according to claim 1 wherein said clock input slack is the maximum slack measured at said pair of clock inputs.
3. The method according to claim 1 wherein said clock input slack is a minimum slack among all tests fed by both of said pair of clock inputs.
4. The method according to claim 1 wherein said clock inputs comprise rising and falling arrival times.
5. The method according to claim 1 wherein said propagating said asserted clock input arrival times includes propagating early and late model clock arrival times.
6. The method according to claim 1 , wherein said at least one pair of clock signals is ordered, and said clock skew slack is dependent on said ordering.
7. The method according to claim 6 , wherein said computation of said clock skew slack includes using early mode arrival times propagated from a first of said pair of clock inputs and late mode arrival times propagated from a second of said clock inputs.
8. The method according to claim 1 wherein said static timing analysis includes gate-level timing.
9. The method according to claim 1 wherein said static timing analysis includes transistor-level timing.
10. The method according to claim 1 wherein said static timing analysis includes propagating statistical distributions.
11. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for conducting a static timing analysis on a top-level design having at least one hierarchical module, the method comprising:
asserting arrival times on a plurality of clock inputs of at least one said hierarchical modules for at least one pair of the plurality of clock inputs;
determining a clock input slack based on propagating asserted clock input arrival times;
determining a largest allowable clock skew as a function of said asserted arrival times at said clock inputs; and
performing a top-level analysis of the hierarchical design, during which said largest allowable clock skew of said at least one pair of clock signals is used to compute a clock skew slack.