Generating a convergent circuit design from a functional description using entities having access to the functional description and to physical design information
View Patent ↗A method of designing a circuit is described. In an embodiment, a physical design implementation for the circuit is created using a plurality of entities. These entities are named “genomes”. Each entity includes a portion of a functional description of the circuit that has been synthesized into a gate-level implementation. An entity is selected to facilitate the physical design implementation meeting a plurality of design constraints. Several steps (e.g., beginning with selection of an entity) of this method are repeated several times to meet the design constraints. As a consequence, the physical design implementation provides more accurate information for use in a final physical design implementation. Moreover, the physical design implementation can be created faster than prior techniques while still allowing a global view of the physical design implementation in meeting design constraints.
1. A method of designing an integrated circuit, comprising:
receiving a functional description that is in a first format of said integrated circuit;
partitioning said functional description that is in said first format into a plurality of entities based on a plurality of rules by using a computer, wherein each entity maintains a respective partition of said functional description in said first format;
synthesizing said functional description that is in said first format of each entity into a gate-level implementation to form a plurality of synthesized entities by using said computer; and
after said synthesizing said functional description that is in said first format, using said plurality of synthesized entities to create a physical design implementation for said integrated circuit that satisfies a plurality of design constraints by using said computer, wherein each synthesized entity includes a link to said respective partition of said functional description that is in said first format and that is synthesized into a respective gate-level implementation, wherein said respective partition of said functional description that is in said first format is accessible for resynthesis by using said link.
2. The method as recited in claim 1 , wherein said using said plurality of synthesized entities to create a physical design implementation for said integrated circuit further comprises:
performing integrated circuit chip level analysis for area, timing and power constraints using aggregate characteristics of said plurality of synthesized entities; and
modifying said plurality of synthesized entities using said integrated circuit chip level analysis to satisfy said design constraints.
3. The method as recited in claim 1 , wherein said using said plurality of synthesized entities comprises: performing place and route operations with said synthesized entities.
4. The method as recited in claim 1 , wherein said using said plurality of synthesized entities comprises: merging a first synthesized entity with a second synthesized entity.
5. The method as recited in claim 1 , wherein said using said plurality of synthesized entities comprises: splitting a synthesized entity into two or more synthesized entities.
6. The method as recited in claim 1 , wherein said using said plurality of synthesized entities comprises: moving a synthesized entity from one location to another location.
7. The method as recited in claim 1 , wherein said using said plurality of synthesized entities comprises: changing size of one or more synthesized entities.
8. The method as recited in claim 1 , wherein said using said plurality of synthesized entities comprises: modifying said gate-level implementation of a synthesized entity.
9. The method as recited in claim 1 , wherein said using said plurality of synthesized entities comprises: resynthesizing functional description of synthesized entity into a new gate-level implementation.
10. The method as recited in claim 1 further comprising: providing a global level view of said physical design implementation using said plurality of synthesized entities to enable said global level view, wherein said global level view ensures satisfying said design constraints.