Integrated circuits with reduced leakage current
View Patent ↗In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.
1. A method of reducing leakage current in an array of circuits, each circuit having an active mode and an inactive mode, each circuit including a set of at least one NMOS transistor, each NMOS transistor in the set having its source connected to a common source node, each NMOS transistor in the set having a gate driven to a ground voltage VSS if its circuit is in the inactive mode, each NMOS transistor in the set being sized so as to conduct a first leakage current if its circuit is in the inactive mode, its source pulled to VSS, and its drain pulled to a power supply voltage VDD, the method comprising:
if all the circuits in the array are in the inactive mode, switching on a first transistor coupled between the common source node and a ground terminal, the first transistor being sized such that the common source node thereby floats higher in potential than VSS to thereby drive the NMOS transistors to conduct a second leakage current that is less than the first leakage current.
2. The method of claim 1 , further comprising:
if one or more of the circuits are to placed into the active mode, switching on a second transistor coupled between the common source node and the ground terminal, the second transistor being sized such that the common source node is thereby pulled to VSS.
3. The method of claim 2 , further comprising:
switching off both the first and the second transistors, whereby the common source node floats in potential towards VDD.
4. A method of reducing leakage current in an array of circuits, each circuit having an active mode and an inactive mode, each circuit including a set of at least one PMOS transistor, each PMOS transistor in the set having its source connected to a common source node, each PMOS transistor in the set having a gate driven to a power supply voltage VDD if its circuit is in the inactive mode, each PMOS transistor in the set being sized so as to conduct a first leakage current if its circuit is in the inactive mode, its source pulled to the power supply voltage VDD, and its drain pulled to ground, the method comprising:
if all the circuits in the array are in the inactive mode, switching on a first transistor coupled between the common source node and a power supply terminal, the first transistor being sized such that the common source node thereby floats lower in potential than VDD to thereby drive the PMOS transistors to conduct a second leakage current that is less than the first leakage current.
5. The method of claim 4 , further comprising:
if one or more of the circuits are to placed into the active mode, switching on a second transistor coupled between the common source node and the power supply terminal, the second transistor being sized such that the common source node is thereby pulled to VDD.
6. The method of claim 5 , further comprising:
switching off both the first and the second transistors, whereby the common source node floats in potential towards VSS.
7. A leakage reduction circuit adapted to reduce leakage for a plurality of NMOS transistors, each NMOS transistor having its source connected to a common source node, each NMOS transistor having a gate driven to a ground voltage VSS if the circuit is in an inactive mode, each NMOS transistor conducting a first leakage current if its circuit is in the inactive mode, its source pulled to VSS, and its drain pulled to a power supply voltage VDD, the circuit comprising:
a first transistor coupled between the common source node and a local ground, the first transistor being adapted to be conductive if the circuit is in the inactive mode, the first transistor being sized such that the common source node thereby floats higher in potential than VSS if the circuit is in the inactive mode to drive the NMOS transistors to conduct a second leakage current that is less than the first leakage current.
8. The leakage reduction circuit of claim 7 , further comprising:
a second transistor coupled between the common source node and the local ground, the second transistor being adapted to be conductive if the circuit is in an active mode, the second transistor having a larger channel than the first transistor.
9. The leakage reduction circuit of claim 8 , wherein both the first and second transistors are NMOS transistors.
10. The leakage reduction circuit of claim 8 , wherein the first NMOS transistor is a diode-connected native NMOS transistor.
11. The leakage reduction circuit of claim 8 , wherein the plurality of NMOS transistors are within a plurality of address decoders.
12. The leakage reduction circuit of claim 8 , wherein the plurality of NMOS transistors are within a plurality of memory cells.
13. The leakage reduction circuit of claim 12 , wherein the plurality of memory cells are SRAM cells.
14. A leakage reduction circuit adapted to reduce leakage for a plurality of PMOS transistors, each PMOS transistor having its source connected to a common source node, each PMOS transistor having a gate driven to a power supply voltage VDD if the circuit is in an inactive mode, each PMOS transistor in the set being sized so as to conduct a first leakage current if its circuit is in the inactive mode, its source pulled to power supply voltage VDD, and its drain pulled to ground, the circuit comprising:
a first transistor coupled between the common source node and a power supply terminal, the first transistor being adapted to be conductive if the circuit is in the inactive mode, the first conductor being sized such that the common source node thereby floats lower in potential than VDD if the circuit is in the inactive mode to drive the PMOS transistors to conduct a second leakage current that is less than the first leakage current.
15. The leakage reduction of claim 14 , further comprising:
a second transistor coupled between the common source node and the power supply terminal, the second transistor being adapted to be conductive if the circuit is in the active mode, the second transistor being sized such that the common source node is thereby pulled to VDD if the circuit is in the active mode.
16. The leakage reduction circuit of claim 15 , wherein both the first and second transistors are PMOS transistors.
17. The leakage reduction circuit of claim 16 , wherein the first PMOS transistor is a diode-connected native PMOS transistor.
18. The leakage reduction circuit of claim 15 , wherein the plurality of PMOS transistors are within a plurality of address decoders.
19. The leakage reduction circuit of claim 15 , wherein the plurality of PMOS transistors are within a plurality of memory cells.
20. The leakage reduction circuit of claim 15 , wherein the plurality of memory cells are SRAM cells.