IP Library Granted Patent US 7,292,098
Granted Patent B2
US 7,292,098 · App. 11/267,422 · Granted Nov 6, 2007

Operational amplifier

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Quick Facts
Patent No.
US 7,292,098
App. No.
11/267,422
Granted
Nov 6, 2007
Kind
B2
Abstract

An operational amplifier is described. The operational amplifier includes a first stage, a second stage, a third stage, and a fourth stage. The amplifier includes a nested transconductance-capacitance compensation configuration. The third stage includes class AB control mechanism. The fourth stage includes a class AB output stage.

Claims (40)

1. An operational amplifier comprising:

an amplifier input for receiving an input signal;

a first stage that includes a first stage input coupled to the amplifier input and a first stage output;

a second stage that includes a second stage input coupled to the first stage output and a second stage output;

a third stage that includes a third stage input coupled to the second stage output, a controller, a first controller bias circuit, a second controller bias circuit and first and second third stage outputs; and

a class AB output stage that includes first and second nodes for receiving the respective first and second third stage outputs and an amplifier output, the first and second outputs from the third stage being in-phase and at different levels, wherein the first stage, second stage, third stage and class AB output stage are configured in a nested compensation structure.

2. The amplifier of claim 1 wherein the nested compensation structure includes a plurality of feed forward paths.

3. The amplifier of claim 2 wherein the plurality of feed forward paths includes

a first feed forward path coupled to the amplifier input and the amplifier output;

a second feed forward path coupled to the second stage input and the amplifier output; and

a third feed forward path coupled to the third stage input and the amplifier output.

4. The amplifier of claim 3 wherein the first feed forward path includes a first feed forward transconductance stage.

5. The amplifier of claim 3 wherein the second feed forward path includes a second feed forward transconductance stage.

6. The amplifier of claim 3 wherein the third feed forward path includes a third feed forward transconductance stage.

7. The amplifier of claim 1 wherein the nested compensation structure includes a plurality of feedback paths.

8. The amplifier of claim 7 wherein the plurality of feedback paths includes

a first feedback path coupled to the second stage input and the amplifier output;

a second feedback path coupled to the third stage input and the amplifier output; and

a third feedback path coupled to the class AB output stage and the amplifier output.

9. The amplifier of claim 8 wherein the first feedback path includes a first compensation capacitor.

10. The amplifier of claim 8 wherein the second feedback path includes a second compensation capacitor.

11. The amplifier of claim 8 wherein the third feedback path includes a third compensation capacitor.

12. The amplifier of claim 1 wherein the first stage includes a differential amplification stage that receives a differential input and generates a single ended output.

13. The amplifier of claim 1 wherein the second stage includes a single field effect transistor (FET).

14. An operational amplifier comprising:

an amplifier input;

an amplifier output; and

a plurality of stages interposed between the amplifier input and the amplifier output, the plurality of stages configured in a frequency compensation structure that improves the stability of the operational amplifier, the plurality of stages including a class AB output stage and a class AB controller that is integrated in one of the stages, the class AB controller configured to generate first and second outputs being in-phase and at different levels to bias the AB output stage.

15. The amplifier of claim 14 wherein the frequency compensation structure includes a plurality of feed forward paths.

16. The amplifier of claim 15 wherein the plurality of feed forward paths includes

a first feed forward path coupled to the amplifier input and the amplifier output;

a second feed forward path coupled to the a second stage input and the amplifier output; and

a third feed forward path coupled to a third stage input and the amplifier output.

17. The amplifier of claim 16 wherein the first feed forward path includes a first feed forward transconductance stage; wherein the second feed forward path includes a second feed forward transconductance stage; and wherein the third feed forward path includes a third feed forward transconductance stage.

18. The amplifier of claim 14 wherein the frequency compensation structure includes a plurality of feedback paths.

19. The amplifier of claim 18 wherein the plurality of feedback paths includes

a first feedback path coupled to a second stage input and the amplifier output;

a second feedback path coupled to a third stage input and the amplifier output; and

a third feedback path coupled to the class AB output stage and the amplifier output.

20. The amplifier of claim 19 wherein the first feedback path includes a first compensation capacitor; wherein the second feedback path includes a second compensation capacitor; and wherein the third feedback path includes a third compensation capacitor.

Assignments (11)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER PREVIOUSLY RECORDED AT REEL: 047357 FRAME: 0302. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048674/0834 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0658. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047357/0302 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0658 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2006
From: CHEN, LEI; LUM, RICHARD KOK KEONG
To: AGILENT TECHNOLOGIES, INC.
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