Semiconductor apparatus and method of manufacturing the same
View Patent ↗A semiconductor apparatus includes a semiconductor substrate of a first conductivity type, a base region of a second conductivity type formed on a principal surface of the semiconductor substrate, a trench formed in a periphery of the base region, and an endless source region of the first conductivity type formed on a surface of the base region along the trench. In this semiconductor apparatus, the principal planes on side surfaces of the trench are composed of planes [100] and [110]. The interior angle of intersection of adjacent side surfaces of the trench is 135°. A minimum distance between the base region and the plane [110] facing each other through the source region is shorter than a minimum distance between the base region and the plane [100] facing each other through the source region.
1. A semiconductor apparatus comprising:
a semiconductor substrate of a first conductivity type;
a base region of a second conductivity type formed on a principal surface of the semiconductor substrate;
a trench having a substantially octagonal plane shape and formed in a periphery of the base region; and
a source region of the first conductivity type formed on a surface of the base region along the trench, wherein
principal planes on side surfaces of the trench are composed of: a first plane [100] that faces the base region through the source region and a second plane [110] that faces the base region through the source region, and
a minimum distance (L 2 ) between the base region and the second plane [110] is shorter than a minimum distance (L 1 ) between the base region and the first plane [100].
2. The semiconductor apparatus according to claim 1 , wherein a planar surface of the source region has a closed shape defined by adjacent side surfaces, wherein an interior angle of intersection of adjacent side surfaces of the trench is substantially 135°.
3. The semiconductor apparatus according to claim 1 , wherein the first plane [100] and the second plane [110] define respective first and second areas, wherein the first area is larger than the second area.
4. The semiconductor apparatus according to claim 1 , wherein the source region includes an electrode connecting area having four sides that are parallel with the first plane [100].
5. A semiconductor apparatus comprising:
a semiconductor substrate of a first conductivity type;
a base region of a second conductivity type formed on a principal surface of the semiconductor substrate;
a trench having a substantially octagonal plane shape and formed in a periphery of the base region; and
a source region of the first conductivity type formed on a surface of the base region along the trench, wherein
principal planes on side surfaces of the trench are composed of: a first plane [100] that faces the base region through the source region and a second plane [110] that faces the base region through the source region,
side surfaces of the trench whose principal planes are composed of the first plane [100] have a first side surface and a second side surface which is perpendicular to the first side surface, and
if lengths of a first side and a second side of the first side surface and the second side surface, respectively, in a horizontal direction with respect to the semiconductor substrate are W 1 and W 3 , a length of a third side of the side surfaces of the trench whose principal planes are composed of the second plane [110] in the horizontal direction with respect to the semiconductor substrate is W 2 , a minimum distance between the second side surface and an opposing second side surface is d, lengths of a fourth side and a fifth side of the base region that are parallel with the first side and the second side, respectively, are Da and Db, an intersection between a perpendicular bisector of the first side and a perpendicular bisector of the second side substantially corresponds to an intersection between a perpendicular bisector of the fourth side and a perpendicular bisector of the fifth side, and following expressions are satisfied:
D b ≧D a
W3≧W1>W2
W 1 =d −√{square root over (2)} ·W 2
W 2>(√{square root over (2)}−1)·( d−D a ).
6. The semiconductor apparatus according to claim 5 , wherein a planar surface of the source region has a closed shape defined by adjacent side surfaces, wherein an interior angle of intersection of adjacent side surfaces of the trench is substantially 135°.
7. The semiconductor apparatus according to claim 5 , wherein the lengths W 1 , W 3 , Da, Db satisfy a following expression:
D b −D a =W 3− W 1≧0.
8. The semiconductor apparatus according to claim 5 , wherein the source region includes an electrode connecting area having four sides that are parallel with the first plane [100].
9. A method of manufacturing a semiconductor apparatus comprising:
forming, on a principal surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer with lower impurity concentration than the semiconductor substrate;
forming a trench in the first semiconductor layer so that principal planes of side surfaces of the trench are composed of: a first plane [100] and a second plane [110];
forming an oxide film by thermally oxidizing an inner surface of the trench;
forming a gate electrode inside the trench with at least the oxide film interposed therebetween;
forming a base region of a second conductivity type on the first semiconductor layer surrounded by the trench; and
forming a source region of the first conductivity type on the base region along the side surface of the trench, wherein
the first plane [100] and the second plane [110] face the base region through the source region, and
a minimum distance between the base region and the second plane [110] is shorter than a minimum distance between the base region and the first plane [100].
10. The method according to claim 9 , wherein:
the side surfaces of the trench whose principal planes are composed of the first plane [100] have a first side surface and a second side surface which is perpendicular to the first side surface, and
if lengths of a first side and a second side of the first side surface and the second side surface, respectively, in a horizontal direction with respect to the semiconductor substrate are W 1 and W 3 , a length of a third side of the side surfaces of the trench whose principal planes are composed of the second plane [110] in the horizontal direction with respect to the semiconductor substrate is W 2 , a minimum distance between the second side surface and an opposing second side surface is d, lengths of a fourth side and a fifth side of the base region that are parallel with the first side and the second side, respectively, are Da and Db, an intersection between a perpendicular bisector of the first side and a perpendicular bisector of the second side substantially corresponds to an intersection between a perpendicular bisector of the fourth side and a perpendicular bisector of the fifth side, and following expressions are satisfied:
D b ≧D a
W3≧W1>W2
W 1 =d −√{square root over (2)}· W 2
W 2>(√{square root over (2)}−1)·( d−D a ).
11. The method according to claim 10 , wherein the lengths W 1 , W 3 , Da, Db satisfy a following expression:
D b −D a =W 3 −W 1≧0.
12. The method according to claim 9 , wherein a planar surface of the source region has a closed shape defined by adjacent side surfaces, wherein an interior angle of intersection of adjacent side surfaces of the trench is substantially 135°.
13. The method according to claim 9 , wherein the source region includes an electrode connecting area having four sides that are parallel with the first plane [100].
14. The method according to claim 9 , wherein the source region has an annular shape that surrounds the base region.
15. The method according to claim 9 , further comprising forming a source electrode on the source region to form a transistor device, wherein the transistor device is configured so that a distance that a dielectric current passes through the base region is shorter than if the minimum distance between the base region and the second plane [110] were not shorter than a minimum distance between the base region and the first plane [100].
16. The semiconductor apparatus according to claim 1 , wherein the source region has an annular shape that surrounds the base region.
17. The semiconductor apparatus according to claim 1 , wherein the semiconductor apparatus comprises a transistor configured so that a distance that a dielectric current passes through the base region is shorter than if the minimum distance (L 2 ) between the base region and the second plane [110] were not shorter than a minimum distance (L 1 ) between the base region and the first plane [100].
18. The semiconductor apparatus according to claim 5 , wherein the source region has an annular shape that surrounds the base region.
19. The semiconductor apparatus according to claim 5 , wherein the semiconductor apparatus comprises a transistor configured so that a distance that a dielectric current passes through the base region is shorter than if the expressions
D b ≧D a
W3≧W1>W2
W 1 =d −√{square root over (2)}· W 2
W 2>(√{square root over (2)}−1)·( d−D a )
were not satisfied.