Synchronous semiconductor storage device having error correction function
A semiconductor memory device has a memory cell array in which a plurality of memory cells are arranged and operates in sync with a clock signal. A read and write operations are performed in the same cycle of the clock signal. The read operation allows the read column selection lines that have been designated by a first column address to connect the read data bus to the bit lines. The write operation allows the write column selection lines that have been designated by a second column address to connect the write data bus to the bit lines. Further, in the write operation, the data obtained by combining the data that has been error-corrected by the syndrome generation circuit and correction circuit with the data that has been input to the input circuit is coded by the code generation circuit and written in the memory cells.
1. A semiconductor memory device which operates in synchronization with a clock signal comprising:
a memory cell array in which a plurality of memory cells are arranged;
a plurality of bit lines connected to the plurality of memory cells;
an input circuit to which data is input;
a code generation circuit which codes data and generates an error correction code;
a read data bus to which the data that has been read out from the memory cells is supplied;
a write data bus to which the data that has been coded by the code generation circuit is supplied;
a plurality of read column selection lines which are designated by a column address and connects the read data bus to the bit lines;
a plurality of write column selection lines which are designated by a column address and connects the write data bus to the bit lines;
a syndrome generation circuit which generates a syndrome from the data that has been read out from the memory cells to the read data bus; and
a correction circuit which decodes the syndrome that has been generated by the syndrome generation circuit and performs an error correction, wherein
a read and write operations are performed in the same cycle of the clock signal, the read operation allowing the read column selection lines that have been designated by a first column address to connect the read data bus to the bit lines, and the write operation allowing the write column selection lines that have been designated by a second column address to connect the write data bus to the bit lines, and
in the write operation, the data obtained by combining the data that has been error-corrected by the syndrome generation circuit and correction circuit with the data that has been input to the input circuit is coded by the code generation circuit and written in the memory cells.
2. The semiconductor memory device according to claim 1 , wherein
the read data bus includes a first and second data buses each with bits width greater than or equal to that of the data coded by the code generation circuit, and
the write data bus includes a third and fourth data buses each with bits width greater than or equal to that of the data coded by the code generation circuit.
3. The semiconductor memory device according to claim 1 , further comprising a storage circuit which is arranged at a stage subsequent to the correction circuit and stores the data that has been output from the correction circuit, wherein
in the case where a read command for performing a read operation has been input after the input of a write command for performing a write operation, if the input column address corresponding to the write command is identical to that corresponding to the read command, the data stored in the storage circuit is output outside thereof as read data.
4. The semiconductor memory device according to claim 1 , wherein
the bits width of the data to be input to the input circuit at the write operation time is smaller than the information length of the error correction code generated by the code generation circuit.
5. A semiconductor memory device which has a burst mode and operates in synchronization with a clock signal comprising:
a memory cell array in which a plurality of memory cells are arranged;
a plurality of bit lines connected to the plurality of memory cells;
an input circuit to which data is input;
a code generation circuit which codes data and generates an error correction code;
a plurality of storage circuits which is arranged at a stage subsequent to the code generation circuit and stores the error correction code that has been output from the code generation circuit;
a first data bus which is connected to the bit lines by column selection lines when even column address has been designated and has bits width greater than or equal to that of the data that has been coded by the code generation circuit;
a second data bus which is connected to the bit lines by column selection lines when odd column address has been designated and has bits width greater than or equal to that of the data that has been coded by the code generation circuit;
a syndrome generation circuit which generates a syndrome from the data that has been read out to the first and second data buses from memory cells; and
a correction circuit which decodes the syndrome that has been generated by the syndrome generation circuit and performs an error correction, wherein
at the read operation time in the burst mode, the data corresponding to odd and even addresses which are generated by the burst are read out from memory cells in the same cycle of the clock signal, subjected to an error correction by the syndrome generation circuit and correction circuit, and output to the outside,
at the write operation time in the burst mode, the data corresponding to odd and even addresses which are generated by the burst are read out from memory cells in the same cycle of the clock signal and subjected to an error correction by the syndrome generation circuit and correction circuit, and the data obtained by combining the data that has been error-corrected with the data that has been input to the input circuit is coded and sequentially written in the storage circuits, and
the data is fetched from the storage circuits that store the data corresponding to the even and odd addresses and written in memory cells in the same cycle of the clock signal through the first and second data buses.
6. The semiconductor memory device according to claim 5 , wherein
the read operation that reads data corresponding to two addresses to the first and second data buses from the memory cells is performed in even-numbered cycles counting from the clock signal cycle at which the read command for performing the read operation has been input, and
the write operation that writes data corresponding to two addresses from the first and second data buses in the memory cells is performed in odd-numbered cycles counting from the clock signal cycle at which the write command for performing the write operation has been input.
7. The semiconductor memory device according to claim 5 , wherein
the bits width of the data to be input to the input circuit at the write operation time is smaller than the information length of the error correction code generated by the code generation circuit.
8. A semiconductor memory device which has a burst mode and performs a pipeline operation in synchronization with a clock signal comprising:
a memory cell array in which a plurality of memory cells are arranged;
a plurality of bit lines connected to the plurality of memory cells;
an input circuit to which data is input;
a code generation circuit which codes data and generates an error correction code;
a plurality of storage circuits which is arranged at a stage subsequent to the code generation circuit and stores the error correction code that has been output from the code generation circuit;
a first data bus which is connected to the bit lines by column selection lines when even column address has been designated and has bits width greater than or equal to that of the data that has been coded by the code generation circuit;
a second data bus which is connected to the bit lines by column selection lines when odd column address has been designated and has bits width greater than or equal to that of the data that has been coded by the code generation circuit;
a syndrome generation circuit which generates a syndrome from the data that has been read out to the first and second data buses from memory cells; and
a correction circuit which decodes the syndrome that has been generated by the syndrome generation circuit and performs an error correction, wherein
the pipeline operation is performed such that,
at the read operation time in the burst mode, data in the memory cells is read out to the first or second data bus depending on whether the current cycle is even-numbered cycle or odd-numbered cycle counting from the clock signal cycle at which the read command for performing the read operation has been input, and the read out data is then error-corrected by the syndrome generation circuit and correction circuit so as to be output to the outside, and
at the write operation time in the burst mode, data in the memory cells is read out to the first or second data bus depending on whether the current cycle is even-numbered cycle or odd-numbered cycle counting from the clock signal cycle at which the write command for performing the write operation has been input, the read out data is then error-corrected by the syndrome generation circuit and correction circuit, and the data obtained by combining the error-corrected data with the data that has been input to the input circuit is coded and sequentially written in the storage circuits so as to be written in the memory cells,
in the above pipeline operation,
a writing operation to the memory cells with respect to odd address is performed when a reading operation from the memory cells with respect to even address is performed, and a writing operation to the memory cells with respect to even address is performed when a reading operation from the memory cells with respect to odd address is performed in the same cycle of the clock signal.
9. The semiconductor memory device according to claim 8 , further comprising: a multiplexer which selects a predetermined number of the storage circuits and outputs the data stored in the selected storage circuits to the first and second data buses.
10. The semiconductor memory device according to claim 8 , wherein
the bits width of the data to be input to the input circuit at the write operation time is smaller than the information length of the error correction code generated by the code generation circuit.