Low hydrogen concentration charge-trapping layer structures for non-volatile memory
Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×10 11 /cm −2 , and methods for forming such memory cells.
1. A memory cell comprising:
a semiconductor substrate having at least two source/drain regions separated by a channel region;
a charge-trapping structure disposed above the channel region; and
a gate disposed above the charge-trapping structure;
wherein the charge-trapping structure comprises:
a top insulating layer disposed under the gate,
a bottom insulating layer disposed between the semiconductor substrate and the top insulating layer;
a second charge-trapping layer consisting of a single layer disposed under and contacting the top insulating layer, and
a first charge-trapping layer disposed between the bottom insulating layer and the second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a plurality of interfacial traps and a hydrogen concentration of less than about 3×10 11 /cm 2 , and a hydrogen concentration of the first charge-trapping layer is lower than a hydrogen concentration of the second charge-trapping layer and the first charge-trapping layer is in contact with the second charge-trapping layer.
2. The memory cell according to claim 1 , wherein the bottom insulating layer has a bulk hydrogen concentration of less than about 6×10 22 /cm 3 .
3. The memory cell according to claim 1 , wherein the first charge-trapping layer has a bulk hydrogen concentration of less than about 6×10 22 /cm 3 .
4. The memory cell according to claim 1 , wherein the bottom insulating layer comprises an oxide, and wherein each of the first charge-trapping layer and the second charge-trapping layer comprises a nitride.
5. The memory cell according to claim 1 , wherein each of the bottom insulating layer and the top insulating layer comprises an oxide, and wherein each of the first charge-trapping layer and the second charge-trapping layer comprises a nitride.
6. The memory cell according to claim 1 , wherein the first charge-trapping layer and the second charge-trapping layer each comprises low-pressure chemical vapor deposited silicon nitride.
7. The memory cell according to claim 1 , wherein an entirety of the single layer is of the same characteristic.
8. The memory cell according to claim 1 , wherein the hydrogen concentration of the first charge-trapping layer is lower than the hydrogen concentration of any portion of the second charge-trapping layer.
9. The memory cell according to claim 1 , wherein a bulk hydrogen concentration of an entirety of the first charge-trapping layer is lower than a bulk hydrogen concentration an entirety of the second charge-trapping layer.