IP Library Granted Patent US 7,989,874
Granted Patent B2
US 7,989,874 · App. 11/275,494 · Granted Aug 2, 2011

Nonvolatile memory device and method for manufacturing the same

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Quick Facts
Patent No.
US 7,989,874
App. No.
11/275,494
Granted
Aug 2, 2011
Kind
B2
Abstract

The present invention discloses a nonvolatile memory device which can improve the data storage capacity without increasing the surface area of the device, and a method for manufacturing the same. The nonvolatile memory device comprises: a gate of a stack type structure formed on an active region of a semiconductor substrate; a source/drain formed in the substrate at both sides of the gate of the stack type structure; an interlayer insulating film formed on the substrate where the source/drain is formed and covering the gate of the stack type structure; a contact connected to the source/drain through the interlayer insulating film; a plurality of conductive patterns formed in the interlayer insulating film of the region not adjacent to the contact; and an electrode pad formed on the conductive patterns.

Claims (20)

1. A nonvolatile memory device, comprising:

a plurality of cell strings arranged in a cell region of a semiconductor substrate, wherein the cell string has a plurality of cell transistors, each cell transistor comprising a gate of a stack type formed on the substrate and a source/drain formed in the substrate at both sides of the gate;

a first interlayer insulating film formed over the substrate where the cell transistors are formed, wherein the interlayer insulating film covers the gate of a stack type;

a second interlayer insulating film formed over the first interlayer insulating film;

a plurality of interconnects formed through the first and second interlayer insulating film, wherein the interconnects are electrically connected to one of the source/drain of the cell transistors;

a plurality of conductive patterns formed in the first and second interlayer insulating films, wherein the conductive patterns do not contact the source/drain of the cell transistors,

wherein one of the conductive pattern is disposed to overlap another source/drain, and

wherein a portion of the first interlayer insulating film is interposed between the one of the conductive patterns and the another source/drain to isolate the one of the conductive patterns from the another source/drain.

2. The nonvolatile memory device of claim 1 , wherein the gate of the stack type structure has a structure in which a floating gate and a control gate are sequentially stacked.

3. The nonvolatile memory device of claim 1 , wherein the interlayer insulating film is formed of an oxide film.

4. The non-volatile memory device of claim 1 , further comprising a BPSG film formed between the interlayer insulating film and the electrode pad.

5. A nonvolatile memory device, comprising:

a semiconductor substrate including active region and isolation region;

first and second gate stacks displaced each other on the active region;

a first junction formed in a portion of the active region between the first and the second gate stacks;

second junctions formed in another portions of the active region relative to the first and second gate stacks opposite to the first junction;

a interlayer insulating film to cover the first and second gate stacks;

first conductive patterns extending through the interlayer insulating film and contacting the second junctions;

second conductive patterns contacting the isolation region; and

a third conductive pattern formed over the first junction by extending partially through the interlayer insulating film, wherein a portion of the interlayer insulating film is disposed between the first junction and the third conductive pattern.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2020
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: KEY FOUNDRY CO., LTD.
Reel/Frame 053703/0227 →