Method for manufacturing a semiconductor device
View Patent ↗A method for manufacturing a semiconductor device includes the steps of preparing a semiconductor substrate, forming a lower electrode having a laminated film of Ir and IrO 2 whose thickness is 100 nm or less over the semiconductor substrate, forming a capacity insulating film comprised of a metal oxide dielectric on the lower electrode, and forming an upper electrode comprised of a precious metal film on the capacity insulating film.
1. A method for manufacturing a semiconductor device, comprising the steps of:
preparing a semiconductor substrate;
forming a lower electrode which is a laminate comprised of a layer of Ir and a layer of IrO 2 over the semiconductor substrate;
forming a capacitor insulating film comprised of a metal oxide dielectric on the lower electrode; and
forming an upper electrode comprised of a precious metal film on the capacitor insulating film,
wherein the Ir film and the IrO 2 film have a combined thickness of 100 nm or less so that leakage current of the semiconductor device is reduced, and
wherein the laminate comprising the lower electrode further comprises a hydrogen diffusion barrier film provided proximate to the semiconductor layer and under a lower surface of-the layer of Ir, and a conductive film comprised of a precious metal provided on the layer of IrO 2 in contact with the capacitor insulating film which functions to reduce Ir diffusion.
2. The method according to claim 1 , wherein the Ir layer has a thickness of 1 nm or more.
3. The method according to claim 1 , wherein the layer of IrO 2 has a thickness of 1 nm or more.
4. The method according to claim 1 , wherein the hydrogen diffusion barrier film is composed of TiAIN.
5. The method according to claim 1 , wherein the precious metal film of the upper electrode consists of Pt.
6. The method according to claim 1 , wherein the precious metal of the conductive film consists of Pt.
7. The method according to claim 1 , wherein the metal oxide dielectric is comprised of one compound selected from the group consisting of a SBT compound, a PZT compound, and a BLT compound.
8. The method according to claim 1 , wherein a laminated film including a layer of TiN and a layer of SiO 2 is used as an etching mask in the steps of forming the lower electrode, forming the capacitor insulating film, and forming the upper electrode.
9. The method according to claim 1 , further comprising the steps of forming a field-effect transistor having a diffusion layer on the semiconductor substrate and connecting the diffusion layer of the field-effect transistor with the lower electrode by means of a plug.
10. A method for manufacturing a semiconductor device, comprising the steps of:
preparing a semiconductor substrate;
forming a lower electrode over the semiconductor substrate which is a laminate;
comprised of, in the order recited, a TiAlN film provided on the semiconductor substrate, an Ir film, an IrO 2 film, and a conductive film consisting of Pt;
forming a capacitor insulating film comprised of a metal oxide dielectric on the lower electrode; and
forming an upper electrode comprised of a precious metal film on the capacitor insulating film,
wherein the Ir film and the IrO 2 film each has a respective thickness of 1 nm or more and have a combined thickness of 100 nm or less so that leakage current of the semiconductor device is reduced.
11. A method for manufacturing a semiconductor device, comprising the steps of:
preparing a semiconductor substrate;
forming a lower electrode over the semiconductor substrate which is a laminate comprised of, in the order recited, a hydrogen diffusion barrier film provided on the semiconductor substrate, an Ir film, an IrO 2 film, and a precious metal film consisting of Pt;
forming a capacity insulating film comprised of a metal oxide dielectric on said lower electrode; and
forming an upper electrode comprised of a precious metal film on said capacity insulating film,
wherein the Ir film and the IrO 2 film each has a respective thickness of 1 nm or more and have a combined thickness of 100 nm or less so that leakage current of the semiconductor device is reduced.