Semiconductor wafer and method for making the same
View Patent ↗A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. WAT pads are disposed along the dicing line. Each of the WAT pads has thereon a slot opening. A reinforcement structure is formed within the slot opening and penetrates through the WAT pad for stopping propagation of de-lamination during wafer dicing.
1. A semiconductor wafer, comprising:
a plurality of active circuit die areas, each of which being bordered by a dicing line through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing;
a plurality of wafer acceptance testing pads in the dicing line, said wafer acceptance testing pad comprising a plurality of dielectric layers; and
a reinforcing structure disposed in said wafer acceptance testing pads, said reinforcing structure comprising a plurality of damascened metal blocking structures in the dielectric layers disposed along at least one side of each said wafer acceptance testing pad for stopping propagation of dielectric de-lamination originating from the mechanical wafer dicing, wherein the bottom of a first damascened metal blocking structure is embedded into an upper dielectric layer and the bottom of a second damascened metal blocking structure is embedded into an underlying dielectric layer of the upper dielectric layer.
2. The semiconductor wafer according to claim 1 wherein the plurality of damascened metal blocking structures comprise at least a row of vias.
3. The semiconductor wafer according to claim 1 wherein the plurality of damascened metal blocking structures comprise at least a via bar.
4. The semiconductor wafer according to claim 1 wherein the plurality of damascened metal blocking structures are filled with metal.
5. The semiconductor wafer according to claim 4 wherein the metal comprises copper.
6. The semiconductor wafer according to claim 1 wherein the plurality of damascened metal blocking structures have air gap therein.
7. The semiconductor wafer according to claim 1 wherein the reinforcing structure is disposed along two sides of each said wafer acceptance testing pad in parallel with the dicing line.