Electrical devices with multi-walled recesses
View Patent ↗The invention relates to a vertical transistor and an oxidation process that achieves a substantially curvilinear recess bottom. The recess serves as the gate receptacle that may facilitate a more uniform gate oxide layer. One embodiment relates to a storage cell that is disposed in the recess along with an electrode. Another embodiment relates to a system that includes the vertical transistor or the vertical storage cell.
1. An electric device, comprising:
a substrate;
a recess in the substrate, the recess being defined by a vertical sidewall and a bottom surface, the bottom surface comprising a horizontal first surface and an inclined, planar second surface intermediate the first surface and the sidewall, the bottom surface including a transition layer intermediate the substrate and a gate dielectric, the transition layer including silicon-deuterium;
a dielectric layer in the recess; and
a conductive layer over the dielectric layer.
2. The electric device of claim 1 , wherein the transition layer includes silicon-hydrogen.
3. The electric device of claim 2 , wherein the dielectric layer includes at least one of a refractory metal oxide, a silicon oxynitride and a silicon nitride.
4. The electric device of claim 1 , wherein the first surface is flat, and wherein the second surface is flat.
5. The electric device of claim 4 , wherein the first surface is at a bottom of the recess.
6. The electric device of claim 1 , wherein the second surface includes a first edge adjacent the first surface and a second edge adjacent the sidewall, the second edge being above the first edge.
7. An electronic device, comprising:
a substrate including a recess defined by a plurality of non-horizontal, planar surfaces, wherein the non-horizontal surfaces are slanted from horizontal, the recess including no horizontal surfaces, the non-horizontal surfaces including a transition layer, the transition layer including at least one of deuterium and hydrogen;
a dielectric layer over the non-horizontal surfaces; and
a conductive layer over the dielectric layer.
8. The electronic device of claim 7 , wherein the substrate includes silicon.
9. The electronic device of claim 7 , wherein the substrate includes an N+ doped source adjacent the recess and an N+ doped drain adjacent the recess.
10. The electronic device of claim 7 , wherein the plurality of surfaces are all non-parallel.
11. The electronic device of claim 7 , wherein the plurality of surfaces are each non-vertical, wherein the non-vertical surfaces are slanted from vertical.
12. The electronic device of claim 7 , wherein a first surface of the plurality of surfaces adjacent a bottom of the recess has an angle relative to horizontal less than a second surface of the plurality of surfaces, the second surface being closer to a top surface of the substrate.
13. An electronic device, comprising:
a substrate including a top surface;
a recess extending downwardly from the top surface, the recess being bound by a plurality of non-horizontal, planar surfaces, wherein the non-horizontal surfaces are slanted from horizontal, the recess including no horizontal surfaces, wherein a first surface of the plurality of surfaces adjacent a bottom of the recess has an angle relative to horizontal less than a second surface of the plurality of surfaces, the second surface being closer to a top surface of the substrate;
a dielectric layer in the recess and extending onto the top surface; and
a conductive layer extending into the recess and on the dielectric layer.
14. The electronic device of claim 13 , wherein the conductive layer is a floating gate.
15. The electronic device of claim 14 , wherein an intergate dielectric is on the floating gate, and wherein a control is on the intergate dielectric.
16. The electronic device of claim 15 , wherein the substrate includes a first doped region adjacent the recess and a second doped region adjacent the recess.
17. The electronic device of claim 16 , wherein the first region and second region are P doped.
18. An electronic device, comprising:
a substrate including a recess defined by a plurality of non-horizontal, planar surfaces, wherein the non-horizontal surfaces are slanted from horizontal, wherein the non-horizontal surfaces include a transition layer including at least one of deuterium and hydrogen;
a dielectric layer over the non-horizontal surfaces; and
a conductive layer over the dielectric layer.
19. The electronic device of claim 18 , wherein the substrate includes silicon.
20. The electronic device of claim 18 , wherein the substrate includes an N+ doped source adjacent the recess and an N+ doped drain adjacent the recess.
21. The electronic device of claim 18 , wherein the plurality of surfaces are each non-vertical, wherein the non-vertical surfaces are slanted from vertical.
22. The electronic device of claim 18 , wherein a first surface of the plurality surfaces adjacent a bottom of the recess has an angle relative to horizontal less than a second surface of the plurality surfaces, the second surface being closer to a top surface of the substrate.
23. An electronic device, comprising:
a substrate including a recess defined by a plurality of non-horizontal, planar surfaces, wherein the non-horizontal surfaces are slanted from horizontal, wherein the plurality of surfaces are all non-parallel, a first surface of the plurality of surfaces adjacent a bottom of the recess having an angle relative to horizontal less than a second surface of the plurality of surfaces, the second surface being closer to a top surface of the substrate;
a dielectric layer over the non-horizontal surfaces; and
a conductive layer over the dielectric layer.
24. The electronic device of claim 23 , wherein the non-horizontal surfaces include a transition layer.
25. The electronic device of claim 23 , wherein the substrate includes an N+ doped source adjacent the recess and an N+ doped drain adjacent the recess.
26. The electronic device of claim 23 , wherein the plurality of surfaces are each non-vertical, wherein the non-vertical surfaces are slanted from vertical.