Memory interface to bridge memory buses
A memory interface to bridge a parallel memory bus and a serial memory bus. A printed circuit board includes at least one memory interface buffer chip to connect a memory controller of core logic and an advanced memory buffer (AMB). The memory controller has a memory interface for a parallel memory bus.
1. A printed circuit board, comprising:
at least one memory interface buffer chip to connect a memory controller of core logic and an advanced memory buffer (AMB), the memory interface buffer chip being separate from the memory controller on the printed circuit board.
2. The printed circuit board of claim 1 , further comprising:
a plurality of memory sockets configured to accept one or more fully buffered memory modules;
a chipset comprising the memory controller; and
a central processing unit (CPU) socket coupled to the chipset to accept a microprocessor chip.
3. The printed circuit board of claim 1 , further comprising:
an advanced memory buffer (AMB) and a plurality of memory chips under the control of the advanced memory buffer.
4. The printed circuit board of claim 1 , wherein the printed circuit board has a form factor suitable for insertion into a memory socket on a motherboard.
5. A computer system, comprising:
a microprocessor chip;
a core logic chip coupled to the microprocessor chip, the core logic chip comprising a memory controller having a memory interface;
one or more fully buffered dual in-line memory modules; and
a memory interface buffer chip coupled between the memory interface of the memory controller and the one or more fully buffered dual in-line memory modules.
6. The computer system of claim 5 , further comprising:
a printed circuit board;
wherein the microprocessor chip, the core logic chip, the one or more fully buffered dual in-line memory modules and the memory buffer chip are mounted on the printed circuit board.
7. The computer system of claim 5 , wherein the memory interface buffer chip is coupled to the memory interface of the memory controller via a bus; and the memory interface buffer chip is not an Advanced Memory Buffer (AMB) of a fully buffered dual in-line memory module.
8. A computer system, comprising:
a microprocessor chip;
a core logic chip coupled to the microprocessor chip, the core logic chip comprising a memory controller;
one or more fully buffered dual in-line memory modules; and
a memory interface buffer chip coupled between the memory controller and the one or more fully buffered dual in-line memory modules, wherein the memory controller accesses memory via a parallel memory bus.
9. The computer system of claim 8 , further comprising:
one or more further buffered dual in-line memory modules; and
a further memory buffer chip coupled between the memory controller and the one or more further fully buffered dual in-line memory modules.
10. A circuit, comprising:
a transceiver to bridge a parallel memory bus and a serial memory bus; and
a protocol converter coupled to the transceiver to translate control signals received from a memory controller of the parallel memory bus to control signals for the serial memory bus.
11. The circuit of claim 10 , wherein the circuit is implemented on a single integrated circuit chip.
12. The circuit of claim 10 , wherein the serial memory bus is connected to an Advanced Memory Buffer (AMB) of a fully buffered dual in-line memory module.
13. The circuit of claim 12 , wherein the parallel memory bus is connected to a memory controller of core logic on a motherboard.
14. The circuit of claim 12 , wherein the parallel memory bus is connected to a memory controller of a northbridge chip.
15. The circuit of claim 10 , wherein the transceiver comprises:
a pseudo differential digital logic circuit to convert an input to the transceiver into a differential digital output.
16. The circuit of claim 15 , wherein the pseudo differential digital logic circuit is implemented using Complementary Metal-Oxide Semiconductor (CMOS).
17. The circuit of claim 16 , further comprising:
an adaptive power-supply regulator coupled with the pseudo differential digital logic circuit to adaptively adjust a power supply of the pseudo differential digital logic circuit.
18. The circuit of claim 16 , wherein the pseudo differential digital logic circuit comprises:
two logic units each of which is one of: a buffer and an inverter; and
a common mode feedback (CMFB) circuit coupled to the two logic units, the CMFB circuit to receive outputs of the two logic units and adjust the two logic units according to a common mode detected from the outputs of the two logic units to suppress command mode.
19. The circuit of claim 16 , wherein the pseudo differential digital logic circuit comprises:
two logic units each of which is one of: a buffer and an inverter; and
a cross couple circuit coupled to the two logic units, the cross couple circuit to cross couple outputs of the two logic units to suppress command mode in the outputs of the two logic units.
20. The circuit of claim 16 , wherein the pseudo differential digital logic circuit comprises:
two logic units each of which is one of: a buffer and an inverter; and
a clock synchronization circuit coupled to the two logic units to synchronize timing of outputs of the two logic units.