Test output compaction for responses with unknown values
A spatial compactor design and technique for the compaction of test response data is herein disclosed which advantageously provides a scan-out response with multiple opportunities to be observed on different output channels in one to several scan-shift cycles.
1. A method of compacting test response data from a circuit, the method comprising:
receiving test response values from a plurality of scan chains and from different scan-shift cycles within a scan chain;
combining the test response values using a plurality of sub-arrays of logic gates thereby directly generating a plurality of output values at a plurality of external outputs, the number of external outputs being less than the number of scan chains, and the sub-arrays of logic gates arranged so as to minimize masking of errors in the test response data.
2. The method of claim 1 wherein the logic gates are XOR gates.
3. The method of claim 1 wherein the test response values in a scan chain are stored in one or more memory elements, thereby providing the plurality of sub-arrays of logic gates with access to test response values from different scan-shift cycles within a scan chain.
4. The method of claim 1 wherein each sub-array can be represented as a Z×C matrix, where Z is the number of external outputs and C is a number of different scan-shift cycles within a scan chain used.
5. The method of claim 4 wherein the matrix representing a sub-array has a same number of logic gates in each column of the matrix and wherein no two matrices are identical.
6. The method of claim 4 wherein there are a fixed number of logic gates within each sub-array and no sub-array is represented by a matrix which is a horizontally-shifted version of another sub-array's matrix.
7. The method of claim 1 wherein the sub-arrays of logic gates are grouped into a plurality of segments such that control signals can be used to block a segment from being combined to one of the plurality of external outputs, the control signals selected so as to minimize masking by unknown values.
8. A logic testing architecture comprising:
a plurality of scan chains;
a plurality of external outputs, the number of external outputs being less than the number of scan chains;
a plurality of sub-arrays of logic gates, each sub-array coupled to a scan chain, the logic gates in a sub-array arranged so as to propagate and combine test response values from different scan-shift cycles within the plurality of scan chains to directly generate output values at each of the external outputs.
9. The logic testing architecture of claim 8 wherein the logic gates are XOR gates.
10. The logic testing architecture of claim 8 wherein each sub-array further comprises one or more memory elements storing test response values from different scan-shift cycles within a scan chain.
11. The logic testing architecture of claim 8 wherein each sub-array can be represented as a Z×C matrix, where Z is the number of external outputs and C is a number of different scan-shift cycles within a scan chain used.
12. The logic testing architecture of claim 11 wherein the matrix representing a sub-array has a same number of logic gates in each column of the matrix and wherein no two matrices are identical.
13. The logic testing architecture of claim 11 wherein there are a fixed number of logic gates within each sub-array and no sub-array is represented by a matrix which is a horizontally-shifted version of another sub-array's matrix.
14. The logic testing architecture of claim 8 wherein the sub-arrays of logic gates are grouped into a plurality of segments such that control signals can be used to block a segment from being combined to one of the plurality of external outputs, the control signals selected so as to minimize masking by unknown values.
15. A logic testing architecture comprising:
a plurality of scan chains;
a plurality of external outputs, the number of external outputs being less than the number of scan chains;
a plurality of logic gates coupling the scan chains to the external outputs, the plurality of logic gates arranged as a time-folding matrix which couples unique sets of external outputs to each scan chain.
16. The logic testing architecture of claim 15 wherein the logic gates are XOR gates.