IP Library Granted Patent US 7,396,717
Granted Patent B2
US 7,396,717 · App. 11/278,434 · Granted Jul 8, 2008

Method of forming a MOS transistor

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Quick Facts
Patent No.
US 7,396,717
App. No.
11/278,434
Granted
Jul 8, 2008
Kind
B2
Abstract

A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect. The implant comprises carbon, a hydrocarbon, or a derivative of the hydrocarbon, such as one selected from a group consisting of C, Chd xH y + , and (C x H y ) n + , wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of 1 to 1000.

Claims (34)

1. A method of forming a MOS transistor, comprising:

providing a substrate having a gate thereon, a source region and a drain region therein with a channel region under the gate therebetween;

thereafter pre-amorphizing the source region and the drain region to form amorphized regions;

thereafter performing a first ion implantation to implant a first dopant in the source region and the drain region to form a first doped region;

thereafter forming at least a spacer on the sidewalls of the gate;

thereafter performing a second ion implantation to implant a second dopant in the source region and the drain region to form a second doped region;

thereafter annealing the source region and the drain region to activate the first dopant, regrow the amorphized regions to a substantially crystalline form, and form a junction profile; and

performing a co-implantation process, after pre-amorphizing the source region and the drain region and before annealing the source region and the drain region, to implant an co-implant in the source region and the drain region, wherein the co-implant comprises C x H y + or (C x H y ) n + , wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of 1 to 1000, and the first dopant comprises B, BF 2 ,B w H z + , or (B w H y ) m + , wherein w is a number of 2 to 30, z is a number of 2 to 40, and m is a number of 10 to 1000.

2. The method claimed as in claim 1 , wherein the co-implant is implanted in the substrate at a place substantially the same as that of the first dopant or the second dopant.

3. The method as claimed in claim 1 , further, after pre-amorphizing the source region and the drain region and before performing the first ion implantation, comprising:

performing a halo implantation to implant a third dopant between the channel region and the source region and between the channel region and the drain region.

4. The method as claimed in claim 3 , wherein the co-implant is implanted in the substrate at a place substantially the same as that of the first dopant, the second dopant, or the third dopant.

5. The method as claimed in claim 3 , wherein the co-implantation process is performed after pre-amorphizing the source region and the drain region and before performing the halo implantation.

6. The method as claimed in claim 3 , wherein the co-implantation process is performed after performing the halo implantation and before performing the first ion implantation.

7. The method as claimed in claim 1 , wherein the co-implantation process is performed after pre-amorphizing the source region and the drain region and before performing the first ion implantation.

8. The method as claimed in claim 1 , wherein the co-implantation process is performed after performing the first implantation and before performing the second ion implantation.

9. The method as claimed in claim 1 , wherein the co-implantation process is performed after performing the second implantation and before annealing the source region and the drain region.

10. A method of forming a MOS transistor, comprising:

providing a substrate having a gate thereon, a source region and a drain region therein with a channel region under the gate therebetween;

pre-amorphizing the source region and the drain region to form amorphized regions;

performing a first ion implantation to implant a first dopant in the source region and the drain region to form a first doped region;

forming at least a spacer on the sidewalls of the gate;

performing a second ion implantation to implant a second dopant in the source region and the drain region to form a second doped region;

annealing the source region and the drain region to activate the first dopant, regrow the amorphized regions to a substantially crystalline form, and form a junction profile; and

performing a co-implantation process, after pre-amorphizing the source region and the drain region and before annealing the source region and the drain region, to implant a co-implant in the source region and the drain region, wherein the co-implant comprises C x H Y + or (C x H y ) n + , wherein x is a number of 1 to 10, y is a number of 4to 20, and n is a number of 1 to 1000, and the first dopant comprises B, BF 2 , B w H z + , or (B w H z ) m + , wherein w is a number of 2 to 30, z is a number of 2 to 40, and m is a number of 10 to 1000.

11. The method as claimed in claim 10 , wherein the co-implant is implanted in the substrate at a place substantially the same as that of the first dopant or the second dopant.

12. The method as claimed in claim 10 , further, after pre-amorphizing the source region and the drain region and before performing the first ion implantation, comprising:

performing a halo implantation to implant a third dopant between the channel region and the source region and between the channel region and the drain region.

13. The method as claimed in claim 12 , wherein the co-implant is implanted in the substrate at a place substantially the same as that of the first dopant, the second dopant, or the third dopant.

14. The method as claimed in claim 12 , wherein the co-implantation process is performed after pre-amorphizing the source region and the drain region and before performing the halo implantation.

15. The method as claimed in claim 12 , wherein the co-implantation process is performed after performing the halo implantation and before performing the first ion implantation.

16. The method as claimed in claim 10 , wherein the co-implantation process is performed after pre-amorphizing the source region and the drain region and before performing the first ion implantation.

17. The method as claimed in claim 10 , wherein the co-implantation process is performed after performing the first implantation and before performing the second ion implantation.

18. The method as claimed in claim 10 , wherein the co-implantation process is performed after performing the second implantation and before annealing the source region and the drain region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2006
From: WANG, HSIANG-YING; CHIEN, CHIN-CHENG; HSIAO, TSAI-FU; CHIEN, MING-YEN; CHEN, CHAO-CHUN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 017412/0342 →