Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation
View Patent ↗A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.
1. A method of manufacturing a semiconductor device having a first and second transistor respectively of an electrostatic discharge protection circuit and internal circuit, the method comprising the steps of:
providing a substrate;
forming gates of the first and second transistor on the substrate;
depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor;
implementing a first ion implantation with a first concentration under the masking of the patterned mask layer;
removing the mask layer and forming sidewall spacers of the gates; and
implementing a second ion implantation with a second concentration, wherein the concentration of the second implantation is heavier than that of the first implantation.
2. The method as claimed in claim 1 , wherein the first ion implantation is N − type ESD implantation.
3. The method as claimed in claim 1 , wherein the second ion implantation is N + type drain diffusion.
4. The method as claimed in claim 1 , wherein the first ion implantation is P − type ESD implantation.
5. The method as claimed in claim 1 , wherein the second ion implantation is P + type drain diffusion.
6. The method as claimed in claim 1 , wherein a layout structure of the first implantation is for a single MOSFET.
7. The method as claimed in claim 1 , wherein a layout structure of the first implantation is for a MOSFET in a stacked configuration structure.
8. The method as claimed in claim 1 , wherein a first depth of the first implantation is larger than that of the second implantation.
9. The method as claimed in claim 1 further comprising the step of:
forming interconnections so that the drain region of the first transistor is coupled to a pad, and the source region and gate of the first transistor is coupled to receive a ground voltage.
10. The method as claimed in claim 1 further comprising the step of:
forming plugs on the gate, drain region and source region of the second transistor.